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2a3fc0c8b2
Context: https://github.com/WebAssembly/memory64/blob/master/proposals/memory64/Overview.md This is just a first step, adding the new instruction variants while keeping the existing 32-bit functionality working. Some of the basic load/store tests have new wasm64 versions that show that the basics of the target are working. Further features need implementation, but these will be added in followups to keep things reviewable. Differential Revision: https://reviews.llvm.org/D80769
45 lines
1.4 KiB
LLVM
45 lines
1.4 KiB
LLVM
; RUN: llc < %s --mtriple=wasm32-unknown-unknown -mattr=+atomics,+sign-ext -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck --check-prefixes CHECK,CHK32 %s
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; RUN: llc < %s --mtriple=wasm64-unknown-unknown -mattr=+atomics,+sign-ext -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck --check-prefixes CHECK,CHK64 %s
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; Test that truncating stores are assembled properly.
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; CHECK-LABEL: trunc_i8_i32:
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; CHECK: i32.atomic.store8 0($0), $1{{$}}
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define void @trunc_i8_i32(i8 *%p, i32 %v) {
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%t = trunc i32 %v to i8
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store atomic i8 %t, i8* %p seq_cst, align 1
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ret void
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}
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; CHECK-LABEL: trunc_i16_i32:
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; CHECK: i32.atomic.store16 0($0), $1{{$}}
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define void @trunc_i16_i32(i16 *%p, i32 %v) {
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%t = trunc i32 %v to i16
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store atomic i16 %t, i16* %p seq_cst, align 2
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ret void
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}
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; CHECK-LABEL: trunc_i8_i64:
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; CHECK: i64.atomic.store8 0($0), $1{{$}}
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define void @trunc_i8_i64(i8 *%p, i64 %v) {
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%t = trunc i64 %v to i8
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store atomic i8 %t, i8* %p seq_cst, align 1
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ret void
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}
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; CHECK-LABEL: trunc_i16_i64:
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; CHECK: i64.atomic.store16 0($0), $1{{$}}
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define void @trunc_i16_i64(i16 *%p, i64 %v) {
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%t = trunc i64 %v to i16
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store atomic i16 %t, i16* %p seq_cst, align 2
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ret void
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}
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; CHECK-LABEL: trunc_i32_i64:
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; CHECK: i64.atomic.store32 0($0), $1{{$}}
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define void @trunc_i32_i64(i32 *%p, i64 %v) {
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%t = trunc i64 %v to i32
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store atomic i32 %t, i32* %p seq_cst, align 4
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ret void
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}
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