mirror of
https://github.com/RPCS3/llvm-mirror.git
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66abdd815e
llvm-svn: 327271
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s
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; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
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; CHECK-LONG: call ##g0@GDPLT
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; CHECK-LONG-NOT: call g0@GDPLT
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; CHECK: call g0@GDPLT
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; CHECK-NOT: call ##g0@GDPLT
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target triple = "hexagon--linux"
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@g0 = internal thread_local global i32 0, align 4
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; Function Attrs: norecurse nounwind
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define void @f0(i32 %a0) local_unnamed_addr #0 {
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b0:
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store volatile i32 1, i32* @g0, align 4, !tbaa !1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define zeroext i1 @f1() local_unnamed_addr #0 {
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b0:
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%v0 = load volatile i32, i32* @g0, align 4, !tbaa !1
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %b2, label %b1
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b1: ; preds = %b0
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store volatile i32 0, i32* @g0, align 4, !tbaa !1
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br label %b2
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b2: ; preds = %b1, %b0
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%v2 = phi i1 [ true, %b1 ], [ false, %b0 ]
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ret i1 %v2
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 7, !"PIC Level", i32 1}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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