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331 lines
14 KiB
LLVM
331 lines
14 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@d = external global <16 x i32>
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; CHECK-LABEL: test1:
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; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test1(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqb.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test2:
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; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test2(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqh.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test3:
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; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test3(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqw.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test4:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test4(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtb.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test5:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test5(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgth.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test6:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test6(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtw.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test7:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
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define void @test7(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtub.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test8:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
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define void @test8(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuh.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test9:
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; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.uw,v{{[0-9]+}}.uw)
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define void @test9(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuw.and(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test10:
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; CHECK: q{{[0-9]}} |= vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test10(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqb.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test11:
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; CHECK: q{{[0-9]}} |= vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test11(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqh.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test12:
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; CHECK: q{{[0-9]}} |= vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test12(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqw.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test13:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test13(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtb.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test14:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test14(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgth.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test15:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test15(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtw.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test16:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
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define void @test16(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtub.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test17:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
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define void @test17(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuh.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test18:
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; CHECK: q{{[0-9]}} |= vcmp.gt(v{{[0-9]+}}.uw,v{{[0-9]+}}.uw)
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define void @test18(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuw.or(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test19:
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; CHECK: q{{[0-9]}} ^= vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test19(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqb.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test20:
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; CHECK: q{{[0-9]}} ^= vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test20(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqh.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test21:
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; CHECK: q{{[0-9]}} ^= vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test21(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.veqw.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test22:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test22(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtb.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test23:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test23(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgth.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test24:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test24(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtw.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test25:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
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define void @test25(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtub.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test26:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
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define void @test26(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuh.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test27:
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; CHECK: q{{[0-9]}} ^= vcmp.gt(v{{[0-9]+}}.uw,v{{[0-9]+}}.uw)
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define void @test27(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <512 x i1>, <512 x i1>* bitcast (<16 x i32>* @d to <512 x i1>*), align 64
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vgtuw.xor(<512 x i1> %0, <16 x i32> %a, <16 x i32> %b)
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%2 = bitcast <512 x i1> %1 to <16 x i32>
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store <16 x i32> %2, <16 x i32>* @d, align 64
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ret void
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}
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declare <512 x i1> @llvm.hexagon.V6.veqb.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqh.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqw.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtb.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgth.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtw.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtub.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuh.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuw.and(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqb.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqh.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqw.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtb.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgth.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtw.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtub.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuh.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuw.or(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqb.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqh.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.veqw.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtb.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgth.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtw.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtub.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuh.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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declare <512 x i1> @llvm.hexagon.V6.vgtuw.xor(<512 x i1>, <16 x i32>, <16 x i32>) #0
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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