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110 lines
3.9 KiB
LLVM
110 lines
3.9 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; Generate REG_SEQUENCE instead of combine
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; CHECK-NOT: combine(#0
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; Function Attrs: nounwind
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define void @f0(i16* nocapture readonly %a0, i16* nocapture readonly %a1, i16* nocapture %a2, i16* nocapture readonly %a3, i32 %a4) #0 {
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b0:
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%v0 = lshr i32 %a4, 1
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %b3, label %b1
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b1: ; preds = %b0
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%v2 = bitcast i16* %a2 to i64*
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%v3 = bitcast i16* %a1 to i64*
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%v4 = bitcast i16* %a0 to i64*
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br label %b2
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b2: ; preds = %b2, %b1
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%v5 = phi i32 [ 0, %b1 ], [ %v71, %b2 ]
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%v6 = phi i64* [ %v4, %b1 ], [ %v9, %b2 ]
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%v7 = phi i64* [ %v3, %b1 ], [ %v11, %b2 ]
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%v8 = phi i64* [ %v2, %b1 ], [ %v70, %b2 ]
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%v9 = getelementptr inbounds i64, i64* %v6, i32 1
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%v10 = load i64, i64* %v6, align 8, !tbaa !0
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%v11 = getelementptr inbounds i64, i64* %v7, i32 1
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%v12 = load i64, i64* %v7, align 8, !tbaa !0
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%v13 = trunc i64 %v10 to i32
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%v14 = lshr i64 %v10, 32
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%v15 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v13)
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%v16 = trunc i64 %v12 to i32
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%v17 = lshr i64 %v12, 32
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%v18 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v16)
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%v19 = trunc i64 %v15 to i32
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%v20 = lshr i64 %v15, 32
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%v21 = getelementptr inbounds i16, i16* %a3, i32 %v19
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%v22 = load i16, i16* %v21, align 2, !tbaa !3
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%v23 = trunc i64 %v20 to i32
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%v24 = getelementptr inbounds i16, i16* %a3, i32 %v23
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%v25 = load i16, i16* %v24, align 2, !tbaa !3
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%v26 = trunc i64 %v18 to i32
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%v27 = lshr i64 %v18, 32
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%v28 = getelementptr inbounds i16, i16* %a3, i32 %v26
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%v29 = load i16, i16* %v28, align 2, !tbaa !3
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%v30 = trunc i64 %v27 to i32
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%v31 = getelementptr inbounds i16, i16* %a3, i32 %v30
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%v32 = load i16, i16* %v31, align 2, !tbaa !3
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%v33 = zext i16 %v32 to i64
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%v34 = shl nuw nsw i64 %v33, 32
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%v35 = zext i16 %v29 to i64
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%v36 = or i64 %v35, %v34
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%v37 = zext i16 %v25 to i64
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%v38 = shl nuw nsw i64 %v37, 32
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%v39 = zext i16 %v22 to i64
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%v40 = or i64 %v39, %v38
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%v41 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v36, i64 %v40)
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%v42 = getelementptr inbounds i64, i64* %v8, i32 1
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store i64 %v41, i64* %v8, align 8, !tbaa !0
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%v43 = trunc i64 %v14 to i32
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%v44 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v43)
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%v45 = trunc i64 %v17 to i32
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%v46 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v45)
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%v47 = trunc i64 %v44 to i32
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%v48 = lshr i64 %v44, 32
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%v49 = getelementptr inbounds i16, i16* %a3, i32 %v47
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%v50 = load i16, i16* %v49, align 2, !tbaa !3
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%v51 = trunc i64 %v48 to i32
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%v52 = getelementptr inbounds i16, i16* %a3, i32 %v51
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%v53 = load i16, i16* %v52, align 2, !tbaa !3
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%v54 = trunc i64 %v46 to i32
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%v55 = lshr i64 %v46, 32
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%v56 = getelementptr inbounds i16, i16* %a3, i32 %v54
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%v57 = load i16, i16* %v56, align 2, !tbaa !3
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%v58 = trunc i64 %v55 to i32
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%v59 = getelementptr inbounds i16, i16* %a3, i32 %v58
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%v60 = load i16, i16* %v59, align 2, !tbaa !3
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%v61 = zext i16 %v60 to i64
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%v62 = shl nuw nsw i64 %v61, 32
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%v63 = zext i16 %v57 to i64
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%v64 = or i64 %v63, %v62
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%v65 = zext i16 %v53 to i64
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%v66 = shl nuw nsw i64 %v65, 32
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%v67 = zext i16 %v50 to i64
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%v68 = or i64 %v67, %v66
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%v69 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v64, i64 %v68)
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%v70 = getelementptr inbounds i64, i64* %v8, i32 2
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store i64 %v69, i64* %v42, align 8, !tbaa !0
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%v71 = add nsw i32 %v5, 1
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%v72 = icmp ult i32 %v71, %v0
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br i1 %v72, label %b2, label %b3
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b3: ; preds = %b2, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vzxthw(i32) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"short", !1, i64 0}
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