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https://github.com/RPCS3/llvm-mirror.git
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2d74f410d9
This is a follow-up to the previous patch that eliminated some of the rotates. With this addition, we will also emit the record-form andis. This patch increases the number of record-form rotates we eliminate by more than 70%. Differential revision: https://reviews.llvm.org/D44897 llvm-svn: 342478
104 lines
3.1 KiB
LLVM
104 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unkknown-unknown \
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; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
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$test = comdat any
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; Function Attrs: noinline nounwind
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define void @test() local_unnamed_addr #0 comdat align 2 {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: cmpdi 1, 3, 0
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; CHECK-NEXT: andi. 4, 3, 3
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; CHECK-NEXT: crand 20, 2, 5
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: addi 3, 3, -1
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; CHECK-NEXT: cmpldi 3, 3
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; CHECK-NEXT: bltlr+ 0
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; CHECK-NEXT: # %bb.1: # %for.body.i.i.i.i.i.i.i
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entry:
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%0 = load float*, float** undef, align 8
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%1 = load i64, i64* undef, align 8
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%add.ptr.i.i.i.i = getelementptr inbounds float, float* %0, i64 undef
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%2 = ptrtoint float* %add.ptr.i.i.i.i to i64
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%and.i.i.i.i.i.i.i = and i64 %2, 3
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%tobool.i.i.i.i.i.i.i = icmp eq i64 %and.i.i.i.i.i.i.i, 0
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%cmp.i.i.i.i.i.i.i = icmp slt i64 0, %1
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%3 = and i1 %tobool.i.i.i.i.i.i.i, %cmp.i.i.i.i.i.i.i
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%spec.select.i.i.i.i.i.i.i = select i1 %3, i64 0, i64 %1
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%4 = add i64 %spec.select.i.i.i.i.i.i.i, -1
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%5 = sub i64 %4, 0
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br label %for.body.i.i.i.i.i.i.i.prol.loopexit
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for.body.i.i.i.i.i.i.i.prol.loopexit: ; preds = %entry
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%6 = icmp ult i64 %5, 3
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br i1 %6, label %exitBB, label %for.body.i.i.i.i.i.i.i
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for.body.i.i.i.i.i.i.i: ; preds = %for.body.i.i.i.i.i.i.i.prol.loopexit
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unreachable
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exitBB: ; preds = %for.body.i.i.i.i.i.i.i.prol.loopexit
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ret void
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}
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define signext i32 @andis_bot(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: andis_bot:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andis. 5, 3, 1
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: isel 4, 4, 5, 2
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%and = and i32 %a, 65536
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%tobool = icmp eq i32 %and, 0
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%mul = select i1 %tobool, i32 %b, i32 1
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%cond = mul nsw i32 %mul, %a
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @andis_mid(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: andis_mid:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andis. 5, 3, 252
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: isel 4, 4, 5, 2
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%and = and i32 %a, 16515072
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%tobool = icmp eq i32 %and, 0
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%mul = select i1 %tobool, i32 %b, i32 1
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%cond = mul nsw i32 %mul, %a
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @andis_top(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: andis_top:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andis. 5, 3, 64512
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: isel 4, 4, 5, 2
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%tobool = icmp ugt i32 %a, 67108863
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%mul = select i1 %tobool, i32 1, i32 %b
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%cond = mul nsw i32 %mul, %a
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ret i32 %cond
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}
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define i64 @andis_no_cmp(i64 %a, i64 %b) {
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entry:
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%and = and i64 %a, 65536
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%tobool = icmp eq i64 %and, 0
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%mul = select i1 %tobool, i64 %b, i64 1
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%cond = mul nsw i64 %mul, %a
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ret i64 %cond
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}
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