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46d19bc0c7
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
61 lines
2.0 KiB
LLVM
61 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
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; Verify internal alignment of long double in a struct. The double
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; argument comes in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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; the long double. Check that these are stored to proper locations
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; in the parameter save area and loaded from there for return in FPR1/2.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.S = type { double, ppc_fp128 }
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define ppc_fp128 @test(%struct.S* byval %x) nounwind {
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entry:
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%b = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1
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%0 = load ppc_fp128, ppc_fp128* %b, align 16
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ret ppc_fp128 %0
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}
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; The additional stores are caused because we forward the value in the
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; store->load->bitcast path to make a store and bitcast of the same
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; value. Since the target does bitcast through memory and we no longer
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; remember the address we need to do the store in a fresh local
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; address.
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; CHECK-DAG: std 6, 72(1)
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; CHECK-DAG: std 5, 64(1)
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; CHECK-DAG: std 4, 56(1)
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; CHECK-DAG: std 3, 48(1)
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; CHECK-DAG: std 5, -16(1)
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; CHECK-DAG: std 6, -8(1)
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; CHECK-DAG: lfd 1, -16(1)
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; CHECK-DAG: lfd 2, -8(1)
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; FIXMECHECK: lfd 1, 64(1)
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; FIXMECHECK: lfd 2, 72(1)
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; CHECK-VSX-DAG: std 6, 72(1)
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; CHECK-VSX-DAG: std 5, 64(1)
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; CHECK-VSX-DAG: std 4, 56(1)
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; CHECK-VSX-DAG: std 3, 48(1)
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; CHECK-VSX-DAG: std 5, -16(1)
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; CHECK-VSX-DAG: std 6, -8(1)
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; CHECK-VSX: lfd 1, -16(1)
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; CHECK-VSX: lfd 2, -8(1)
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; FIXME-VSX: addi 4, 1, 48
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; FIXME-VSX: lxsdx 1, 4, 3
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; FIXME-VSX: li 3, 24
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; FIXME-VSX: lxsdx 2, 4, 3
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; CHECK-P9-DAG: std 6, 72(1)
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; CHECK-P9-DAG: std 5, 64(1)
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; CHECK-P9-DAG: std 4, 56(1)
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; CHECK-P9-DAG: std 3, 48(1)
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; CHECK-P9-DAG: mtvsrd 1, 5
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; CHECK-P9-DAG: mtvsrd 2, 6
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