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fbdbebb240
The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 llvm-svn: 320473
113 lines
3.2 KiB
LLVM
113 lines
3.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i8 0, align 1
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp uge i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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; CHECK-LABEL: test_igeuc:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
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; CHECK-NEXT: xori r3, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp uge i8 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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; CHECK-LABEL: @test_igeuc_sext
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igeuc_z(i8 zeroext %a) {
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entry:
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%cmp = icmp uge i8 %a, 0
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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; CHECK-LABEL: @test_igeuc_z
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; CHECK: li r3, 1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
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entry:
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%cmp = icmp uge i8 %a, 0
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%conv2 = sext i1 %cmp to i32
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ret i32 %conv2
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; CHECK-LABEL: @test_igeuc_sext_z
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; CHECK: li r3, -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp uge i8 %a, %b
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK_LABEL: test_igeuc_store:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
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; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp uge i8 %a, %b
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK-TBD-LABEL: @test_igeuc_sext_store
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; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4
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; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK-TBD: stb [[REG3]]
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; CHECK-TBD: blr
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}
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; Function Attrs : norecurse nounwind
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define void @test_igeuc_z_store(i8 zeroext %a) {
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entry:
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%cmp = icmp uge i8 %a, 0
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK-LABEL: @test_igeuc_z_store
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; CHECK: li [[REG1:r[0-9]+]], 1
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; CHECK: stb [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_igeuc_sext_z_store(i8 zeroext %a) {
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entry:
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%cmp = icmp uge i8 %a, 0
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK-LABEL: @test_igeuc_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: stb [[REG1]]
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; CHECK: blr
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}
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