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llvm-mirror/test/CodeGen/SPARC/spill.ll
James Y Knight 2a6af41342 [Sparc] Implement i64 load/store support for 32-bit sparc.
The LDD/STD instructions can load/store a 64bit quantity from/to
memory to/from a consecutive even/odd pair of (32-bit) registers. They
are part of SparcV8, and also present in SparcV9. (Although deprecated
there, as you can store 64bits in one register).

As recommended on llvmdev in the thread "How to enable use of 64bit
load/store for 32bit architecture" from Apr 2015, I've modeled the
64-bit load/store operations as working on a v2i32 type, rather than
making i64 a legal type, but with few legal operations. The latter
does not (currently) work, as there is much code in llvm which assumes
that if i64 is legal, operations like "add" will actually work on it.

The same assumption does not hold for v2i32 -- for vector types, it is
workable to support only load/store, and expand everything else.

This patch:
- Adds a new register class, IntPair, for even/odd pairs of registers.

- Modifies the list of reserved registers, the stack spilling code,
  and register copying code to support the IntPair register class.

- Adds support in AsmParser. (note that in asm text, you write the
  name of the first register of the pair only. So the parser has to
  morph the single register into the equivalent paired register).

- Adds the new instructions themselves (LDD/STD/LDDA/STDA).

- Hooks up the instructions and registers as a vector type v2i32. Adds
  custom legalizer to transform i64 load/stores into v2i32 load/stores
  and bitcasts, so that the new instructions can actually be
  generated, and marks all operations other than load/store on v2i32
  as needing to be expanded.

- Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG.
  This hack undoes the transformation of i64 operands into two
  arbitrarily-allocated separate i32 registers in
  SelectionDAGBuilder. and instead passes them in a single
  IntPair. (Arbitrarily allocated registers are not useful, asm code
  expects to be receiving a pair, which can be passed to ldd/std.)

Also adds a bunch of test cases covering all the bugs I've added along
the way.

Differential Revision: http://reviews.llvm.org/D8713

llvm-svn: 244484
2015-08-10 19:11:39 +00:00

65 lines
2.2 KiB
LLVM

; RUN: llc -march=sparc < %s | FileCheck %s
;; Ensure that spills and reloads work for various types on
;; sparcv8.
;; For i32/i64 tests, use an asm statement which clobbers most
;; registers to ensure the spill will happen.
; CHECK-LABEL: test_i32_spill:
; CHECK: and %i0, %i1, %o0
; CHECK: st %o0, [%fp+{{.+}}]
; CHECK: add %o0, %o0, %g0
; CHECK: ld [%fp+{{.+}}, %i0
define i32 @test_i32_spill(i32 %a, i32 %b) {
entry:
%r0 = and i32 %a, %b
; The clobber list has all registers except g0/o0. (Only o0 is usable.)
%0 = call i32 asm sideeffect "add $0,$1,%g0", "=r,0,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7}"(i32 %r0)
ret i32 %r0
}
; CHECK-LABEL: test_i64_spill:
; CHECK: and %i0, %i2, %o0
; CHECK: and %i1, %i3, %o1
; CHECK: std %o0, [%fp+{{.+}}]
; CHECK: add %o0, %o0, %g0
; CHECK: ldd [%fp+{{.+}}, %i0
define i64 @test_i64_spill(i64 %a, i64 %b) {
entry:
%r0 = and i64 %a, %b
; The clobber list has all registers except g0,g1,o0,o1. (Only o0/o1 are a usable pair)
; So, o0/o1 must be used.
%0 = call i64 asm sideeffect "add $0,$1,%g0", "=r,0,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o2},~{o3},~{o4},~{o5},~{o7}"(i64 %r0)
ret i64 %r0
}
;; For float/double tests, a call is a suitable clobber as *all* FPU
;; registers are caller-save on sparcv8.
; CHECK-LABEL: test_float_spill:
; CHECK: fadds %f1, %f0, [[R:%[f][0-31]]]
; CHECK: st [[R]], [%fp+{{.+}}]
; CHECK: call
; CHECK: ld [%fp+{{.+}}, %f0
declare float @foo_float(float)
define float @test_float_spill(float %a, float %b) {
entry:
%r0 = fadd float %a, %b
%0 = call float @foo_float(float %r0)
ret float %r0
}
; CHECK-LABEL: test_double_spill:
; CHECK: faddd %f2, %f0, [[R:%[f][0-31]]]
; CHECK: std [[R]], [%fp+{{.+}}]
; CHECK: call
; CHECK: ldd [%fp+{{.+}}, %f0
declare double @foo_double(double)
define double @test_double_spill(double %a, double %b) {
entry:
%r0 = fadd double %a, %b
%0 = call double @foo_double(double %r0)
ret double %r0
}