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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
65 lines
1.8 KiB
LLVM
65 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X64
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,WIN64
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; PR8573
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define void @foo(i8* %P, i32 %E, i32 %H) nounwind {
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; X86-LABEL: foo:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: leal (%eax), %eax
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; X86-NEXT: monitor
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; X86-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl %esi, %ecx
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; X64-NEXT: leaq (%rdi), %rax
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; X64-NEXT: monitor
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; X64-NEXT: retq
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;
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; WIN64-LABEL: foo:
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; WIN64: # %bb.0: # %entry
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; WIN64-NEXT: leaq (%rcx), %rax
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; WIN64-NEXT: movl %edx, %ecx
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; WIN64-NEXT: movl %r8d, %edx
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; WIN64-NEXT: monitor
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; WIN64-NEXT: retq
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entry:
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tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
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define void @bar(i32 %E, i32 %H) nounwind {
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; X86-LABEL: bar:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: mwait
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; X86-NEXT: retl
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;
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; X64-LABEL: bar:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: mwait
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; X64-NEXT: retq
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;
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; WIN64-LABEL: bar:
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; WIN64: # %bb.0: # %entry
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; WIN64-NEXT: movl %edx, %eax
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; WIN64-NEXT: mwait
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; WIN64-NEXT: retq
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entry:
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tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
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