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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
61 lines
2.0 KiB
LLVM
61 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-linux-gnu < %s | FileCheck %s
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%"struct.std::atomic" = type { %"struct.std::atomic_bool" }
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%"struct.std::atomic_bool" = type { %"struct.std::__atomic_base" }
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%"struct.std::__atomic_base" = type { i8 }
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; CHECK-LABEL: _Z3fooRSt6atomicIbEb
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define zeroext i1 @_Z3fooRSt6atomicIbEb(%"struct.std::atomic"* nocapture dereferenceable(1) %a, i1 returned zeroext %b) nounwind {
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; CHECK-LABEL: _Z3fooRSt6atomicIbEb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movq %rdi, %rcx
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; CHECK-NEXT: shrq $3, %rcx
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; CHECK-NEXT: movb 2147450880(%rcx), %cl
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; CHECK-NEXT: testb %cl, %cl
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; CHECK-NEXT: je .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: andl $7, %edx
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; CHECK-NEXT: cmpb %cl, %dl
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; CHECK-NEXT: jge .LBB0_2
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: xchgb %cl, (%rdi)
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: callq __asan_report_store1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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entry:
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%frombool.i.i = zext i1 %b to i8
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%_M_i.i.i = getelementptr inbounds %"struct.std::atomic", %"struct.std::atomic"* %a, i64 0, i32 0, i32 0, i32 0
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%0 = ptrtoint i8* %_M_i.i.i to i64
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%1 = lshr i64 %0, 3
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%2 = add i64 %1, 2147450880
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%3 = inttoptr i64 %2 to i8*
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%4 = load i8, i8* %3
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%5 = icmp ne i8 %4, 0
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br i1 %5, label %6, label %11
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; <label>:6: ; preds = %entry
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%7 = and i64 %0, 7
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%8 = trunc i64 %7 to i8
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%9 = icmp sge i8 %8, %4
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br i1 %9, label %10, label %11
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; <label>:10: ; preds = %6
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call void @__asan_report_store1(i64 %0)
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call void asm sideeffect "", ""()
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unreachable
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; <label>:11: ; preds = %6, %entry
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store atomic i8 %frombool.i.i, i8* %_M_i.i.i seq_cst, align 1
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ret i1 %b
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}
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declare void @__asan_report_store1(i64)
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