Sam Parker c43926770c [ARM][AArch64] v8.3-A Javascript Conversion ... Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 llvm-svn: 311448		2017-08-22 11:08:21 +00:00
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AArch64	[ARM][AArch64] v8.3-A Javascript Conversion	2017-08-22 11:08:21 +00:00
AMDGPU	[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16	2017-08-16 15:16:32 +00:00
ARM	[ARM][AArch64] v8.3-A Javascript Conversion	2017-08-22 11:08:21 +00:00
Hexagon	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""	2017-08-14 16:20:33 +00:00
PowerPC	[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.	2017-06-12 17:58:42 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	[X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility.	2017-07-22 01:30:53 +00:00
XCore