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3d518334b9
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary search tree of basic blocks. The new approach has several advantages: it is faster, it generates significantly smaller code in many cases, and it paves the way for implementing dense switch tables as a jump table by handling switches directly in the instruction selector. This functionality is currently only enabled on x86, but should be safe for every target. In anticipation of making it the default, the cfg is now properly updated in the x86, ppc, and sparc select lowering code. llvm-svn: 27156
122 lines
4.6 KiB
C++
122 lines
4.6 KiB
C++
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#include "llvm/Pass.h"
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#include "llvm/Constant.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class SelectionDAG;
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class SelectionDAGLowering;
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class SDOperand;
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class SSARegMap;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class TargetLowering;
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class FunctionLoweringInfo;
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class HazardRecognizer;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public FunctionPass {
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public:
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TargetLowering &TLI;
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SSARegMap *RegMap;
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SelectionDAG *CurDAG;
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MachineBasicBlock *BB;
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SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnFunction(Function &Fn);
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unsigned MakeReg(MVT::ValueType VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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return true;
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}
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// to use for this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer();
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/// CaseBlock - This structure is used to communicate between SDLowering and
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
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MachineBasicBlock *rhs, MachineBasicBlock *me) :
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CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// SwitchV - the value to be switched on, 'foo' in switch(foo)
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Value *SwitchV;
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// CaseC - the constant the setcc node will compare against SwitchV
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Constant *CaseC;
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// LHSBB - the block to branch to if the setcc is true
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MachineBasicBlock *LHSBB;
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// RHSBB - the block to branch to if the setcc is false
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MachineBasicBlock *RHSBB;
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// ThisBB - the blcok into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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protected:
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &DAG);
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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private:
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SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
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Value *V, unsigned Reg);
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void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
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FunctionLoweringInfo &FuncInfo);
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void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
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FunctionLoweringInfo &FuncInfo);
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void CodeGenAndEmitDAG(SelectionDAG &DAG);
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void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
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std::vector<SDOperand> &UnorderedChains);
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<CaseBlock> SwitchCases;
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
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