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llvm-mirror/docs/AMDGPU/gfx9_imm4.rst
Dmitry Preobrazhensky ce9abb7e3a [AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368
2018-12-17 17:38:11 +00:00

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.. _amdgpu_synid9_imm4:
imm4
===========================
A positive :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 4 bits.
This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it.
============ ========================================
Bit Meaning
============ ========================================
0 Enables or disables *src0* indexing.
1 Enables or disables *src1* indexing.
2 Enables or disables *src2* indexing.
3 Enables or disables *dst* indexing.
============ ========================================