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343 lines
13 KiB
C++
343 lines
13 KiB
C++
//===-------- SplitKit.h - Toolkit for splitting live ranges ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SplitAnalysis class as well as mutator functions for
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// live range splitting.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/IntervalMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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namespace llvm {
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class ConnectedVNInfoEqClasses;
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class LiveInterval;
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class LiveIntervals;
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class LiveRangeEdit;
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class MachineInstr;
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class MachineLoopInfo;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class VirtRegMap;
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class VNInfo;
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class raw_ostream;
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/// At some point we should just include MachineDominators.h:
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class MachineDominatorTree;
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template <class NodeT> class DomTreeNodeBase;
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typedef DomTreeNodeBase<MachineBasicBlock> MachineDomTreeNode;
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/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
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/// opportunities.
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class SplitAnalysis {
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public:
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const MachineFunction &MF;
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const VirtRegMap &VRM;
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const LiveIntervals &LIS;
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const MachineLoopInfo &Loops;
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const TargetInstrInfo &TII;
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// Instructions using the the current register.
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typedef SmallPtrSet<const MachineInstr*, 16> InstrPtrSet;
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InstrPtrSet UsingInstrs;
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// Sorted slot indexes of using instructions.
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SmallVector<SlotIndex, 8> UseSlots;
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// The number of instructions using CurLI in each basic block.
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typedef DenseMap<const MachineBasicBlock*, unsigned> BlockCountMap;
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BlockCountMap UsingBlocks;
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/// Additional information about basic blocks where the current variable is
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/// live. Such a block will look like one of these templates:
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///
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/// 1. | o---x | Internal to block. Variable is only live in this block.
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/// 2. |---x | Live-in, kill.
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/// 3. | o---| Def, live-out.
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/// 4. |---x o---| Live-in, kill, def, live-out.
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/// 5. |---o---o---| Live-through with uses or defs.
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/// 6. |-----------| Live-through without uses. Transparent.
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///
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struct BlockInfo {
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MachineBasicBlock *MBB;
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SlotIndex Start; ///< Beginining of block.
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SlotIndex Stop; ///< End of block.
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SlotIndex FirstUse; ///< First instr using current reg.
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SlotIndex LastUse; ///< Last instr using current reg.
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SlotIndex Kill; ///< Interval end point inside block.
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SlotIndex Def; ///< Interval start point inside block.
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/// Last possible point for splitting live ranges.
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SlotIndex LastSplitPoint;
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bool Uses; ///< Current reg has uses or defs in block.
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bool LiveThrough; ///< Live in whole block (Templ 5. or 6. above).
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bool LiveIn; ///< Current reg is live in.
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bool LiveOut; ///< Current reg is live out.
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// Per-interference pattern scratch data.
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bool OverlapEntry; ///< Interference overlaps entering interval.
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bool OverlapExit; ///< Interference overlaps exiting interval.
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};
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/// Basic blocks where var is live. This array is parallel to
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/// SpillConstraints.
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SmallVector<BlockInfo, 8> LiveBlocks;
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private:
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// Current live interval.
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const LiveInterval *CurLI;
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// Sumarize statistics by counting instructions using CurLI.
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void analyzeUses();
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/// calcLiveBlockInfo - Compute per-block information about CurLI.
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bool calcLiveBlockInfo();
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/// canAnalyzeBranch - Return true if MBB ends in a branch that can be
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/// analyzed.
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bool canAnalyzeBranch(const MachineBasicBlock *MBB);
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public:
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SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
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const MachineLoopInfo &mli);
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/// analyze - set CurLI to the specified interval, and analyze how it may be
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/// split.
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void analyze(const LiveInterval *li);
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/// clear - clear all data structures so SplitAnalysis is ready to analyze a
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/// new interval.
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void clear();
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/// getParent - Return the last analyzed interval.
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const LiveInterval &getParent() const { return *CurLI; }
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/// hasUses - Return true if MBB has any uses of CurLI.
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bool hasUses(const MachineBasicBlock *MBB) const {
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return UsingBlocks.lookup(MBB);
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}
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/// isOriginalEndpoint - Return true if the original live range was killed or
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/// (re-)defined at Idx. Idx should be the 'def' slot for a normal kill/def,
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/// and 'use' for an early-clobber def.
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/// This can be used to recognize code inserted by earlier live range
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/// splitting.
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bool isOriginalEndpoint(SlotIndex Idx) const;
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typedef SmallPtrSet<const MachineBasicBlock*, 16> BlockPtrSet;
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// Print a set of blocks with use counts.
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void print(const BlockPtrSet&, raw_ostream&) const;
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/// getMultiUseBlocks - Add basic blocks to Blocks that may benefit from
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/// having CurLI split to a new live interval. Return true if Blocks can be
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/// passed to SplitEditor::splitSingleBlocks.
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bool getMultiUseBlocks(BlockPtrSet &Blocks);
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};
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/// SplitEditor - Edit machine code and LiveIntervals for live range
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/// splitting.
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///
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/// - Create a SplitEditor from a SplitAnalysis.
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/// - Start a new live interval with openIntv.
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/// - Mark the places where the new interval is entered using enterIntv*
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/// - Mark the ranges where the new interval is used with useIntv*
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/// - Mark the places where the interval is exited with exitIntv*.
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/// - Finish the current interval with closeIntv and repeat from 2.
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/// - Rewrite instructions with finish().
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///
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class SplitEditor {
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SplitAnalysis &SA;
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LiveIntervals &LIS;
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VirtRegMap &VRM;
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MachineRegisterInfo &MRI;
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MachineDominatorTree &MDT;
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const TargetInstrInfo &TII;
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const TargetRegisterInfo &TRI;
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/// Edit - The current parent register and new intervals created.
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LiveRangeEdit *Edit;
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/// Index into Edit of the currently open interval.
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/// The index 0 is used for the complement, so the first interval started by
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/// openIntv will be 1.
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unsigned OpenIdx;
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typedef IntervalMap<SlotIndex, unsigned> RegAssignMap;
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/// Allocator for the interval map. This will eventually be shared with
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/// SlotIndexes and LiveIntervals.
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RegAssignMap::Allocator Allocator;
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/// RegAssign - Map of the assigned register indexes.
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/// Edit.get(RegAssign.lookup(Idx)) is the register that should be live at
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/// Idx.
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RegAssignMap RegAssign;
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typedef DenseMap<std::pair<unsigned, unsigned>, VNInfo*> ValueMap;
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/// Values - keep track of the mapping from parent values to values in the new
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/// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
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///
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/// 1. No entry - the value is not mapped to Edit.get(RegIdx).
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/// 2. Null - the value is mapped to multiple values in Edit.get(RegIdx).
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/// Each value is represented by a minimal live range at its def.
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/// 3. A non-null VNInfo - the value is mapped to a single new value.
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/// The new value has no live ranges anywhere.
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ValueMap Values;
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typedef std::pair<VNInfo*, MachineDomTreeNode*> LiveOutPair;
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typedef IndexedMap<LiveOutPair, MBB2NumberFunctor> LiveOutMap;
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// LiveOutCache - Map each basic block where a new register is live out to the
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// live-out value and its defining block.
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// One of these conditions shall be true:
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//
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// 1. !LiveOutCache.count(MBB)
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// 2. LiveOutCache[MBB].second.getNode() == MBB
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// 3. forall P in preds(MBB): LiveOutCache[P] == LiveOutCache[MBB]
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//
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// This is only a cache, the values can be computed as:
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//
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// VNI = Edit.get(RegIdx)->getVNInfoAt(LIS.getMBBEndIdx(MBB))
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// Node = mbt_[LIS.getMBBFromIndex(VNI->def)]
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//
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// The cache is also used as a visited set by extendRange(). It can be shared
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// by all the new registers because at most one is live out of each block.
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LiveOutMap LiveOutCache;
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// LiveOutSeen - Indexed by MBB->getNumber(), a bit is set for each valid
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// entry in LiveOutCache.
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BitVector LiveOutSeen;
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/// defValue - define a value in RegIdx from ParentVNI at Idx.
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/// Idx does not have to be ParentVNI->def, but it must be contained within
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/// ParentVNI's live range in ParentLI. The new value is added to the value
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/// map.
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/// Return the new LI value.
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VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
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/// markComplexMapped - Mark ParentVNI as complex mapped in RegIdx regardless
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/// of the number of defs.
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void markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI);
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/// defFromParent - Define Reg from ParentVNI at UseIdx using either
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/// rematerialization or a COPY from parent. Return the new value.
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VNInfo *defFromParent(unsigned RegIdx,
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VNInfo *ParentVNI,
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SlotIndex UseIdx,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I);
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/// extendRange - Extend the live range of Edit.get(RegIdx) so it reaches Idx.
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/// Insert PHIDefs as needed to preserve SSA form.
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void extendRange(unsigned RegIdx, SlotIndex Idx);
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/// updateSSA - Insert PHIDefs as necessary and update LiveOutCache such that
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/// Edit.get(RegIdx) is live-in to all the blocks in LiveIn.
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/// Return the value that is eventually live-in to IdxMBB.
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VNInfo *updateSSA(unsigned RegIdx,
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SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
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SlotIndex Idx,
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const MachineBasicBlock *IdxMBB);
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/// transferSimpleValues - Transfer simply defined values to the new ranges.
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/// Return true if any complex ranges were skipped.
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bool transferSimpleValues();
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/// extendPHIKillRanges - Extend the ranges of all values killed by original
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/// parent PHIDefs.
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void extendPHIKillRanges();
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/// rewriteAssigned - Rewrite all uses of Edit.getReg() to assigned registers.
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void rewriteAssigned(bool ExtendRanges);
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/// deleteRematVictims - Delete defs that are dead after rematerializing.
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void deleteRematVictims();
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public:
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/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
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/// Newly created intervals will be appended to newIntervals.
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SplitEditor(SplitAnalysis &SA, LiveIntervals&, VirtRegMap&,
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MachineDominatorTree&);
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/// reset - Prepare for a new split.
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void reset(LiveRangeEdit&);
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/// Create a new virtual register and live interval.
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void openIntv();
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/// enterIntvBefore - Enter the open interval before the instruction at Idx.
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/// If the parent interval is not live before Idx, a COPY is not inserted.
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/// Return the beginning of the new live range.
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SlotIndex enterIntvBefore(SlotIndex Idx);
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/// enterIntvAtEnd - Enter the open interval at the end of MBB.
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/// Use the open interval from he inserted copy to the MBB end.
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/// Return the beginning of the new live range.
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SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB);
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/// useIntv - indicate that all instructions in MBB should use OpenLI.
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void useIntv(const MachineBasicBlock &MBB);
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/// useIntv - indicate that all instructions in range should use OpenLI.
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void useIntv(SlotIndex Start, SlotIndex End);
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/// leaveIntvAfter - Leave the open interval after the instruction at Idx.
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/// Return the end of the live range.
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SlotIndex leaveIntvAfter(SlotIndex Idx);
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/// leaveIntvBefore - Leave the open interval before the instruction at Idx.
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/// Return the end of the live range.
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SlotIndex leaveIntvBefore(SlotIndex Idx);
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/// leaveIntvAtTop - Leave the interval at the top of MBB.
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/// Add liveness from the MBB top to the copy.
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/// Return the end of the live range.
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SlotIndex leaveIntvAtTop(MachineBasicBlock &MBB);
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/// overlapIntv - Indicate that all instructions in range should use the open
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/// interval, but also let the complement interval be live.
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///
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/// This doubles the register pressure, but is sometimes required to deal with
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/// register uses after the last valid split point.
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///
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/// The Start index should be a return value from a leaveIntv* call, and End
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/// should be in the same basic block. The parent interval must have the same
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/// value across the range.
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///
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void overlapIntv(SlotIndex Start, SlotIndex End);
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/// closeIntv - Indicate that we are done editing the currently open
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/// LiveInterval, and ranges can be trimmed.
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void closeIntv();
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/// finish - after all the new live ranges have been created, compute the
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/// remaining live range, and rewrite instructions to use the new registers.
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void finish();
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/// dump - print the current interval maping to dbgs().
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void dump() const;
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// ===--- High level methods ---===
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/// splitSingleBlocks - Split CurLI into a separate live interval inside each
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/// basic block in Blocks.
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void splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks);
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};
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}
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