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3f7c3f8303
This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
83 lines
2.8 KiB
C++
83 lines
2.8 KiB
C++
//===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#define GET_REGBANK_DECLARATIONS
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#include "X86GenRegisterBank.inc"
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namespace llvm {
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class LLT;
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class X86GenRegisterBankInfo : public RegisterBankInfo {
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protected:
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#define GET_TARGET_REGBANK_CLASS
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#include "X86GenRegisterBank.inc"
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#define GET_TARGET_REGBANK_INFO_CLASS
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#include "X86GenRegisterBankInfo.def"
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static RegisterBankInfo::PartialMapping PartMappings[];
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static RegisterBankInfo::ValueMapping ValMappings[];
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static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
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static const RegisterBankInfo::ValueMapping *
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getValueMapping(PartialMappingIdx Idx, unsigned NumOperands);
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};
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class TargetRegisterInfo;
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/// This class provides the information for the target register banks.
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class X86RegisterBankInfo final : public X86GenRegisterBankInfo {
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private:
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/// Get an instruction mapping.
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/// \return An InstructionMappings with a statically allocated
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/// OperandsMapping.
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const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI,
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bool isFP) const;
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/// Track the bank of each instruction operand(register)
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static void
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getInstrPartialMappingIdxs(const MachineInstr &MI,
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const MachineRegisterInfo &MRI, const bool isFP,
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SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx);
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/// Construct the instruction ValueMapping from PartialMappingIdxs
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/// \return true if mapping succeeded.
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static bool
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getInstrValueMapping(const MachineInstr &MI,
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const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
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SmallVectorImpl<const ValueMapping *> &OpdsMapping);
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public:
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X86RegisterBankInfo(const TargetRegisterInfo &TRI);
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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InstructionMappings
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getInstrAlternativeMappings(const MachineInstr &MI) const override;
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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const InstructionMapping &
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getInstrMapping(const MachineInstr &MI) const override;
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};
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} // namespace llvm
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#endif
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