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b046734bb1
Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=16439. This is one possible way to approach this. The other would be to split InL>>(nbits-Amt) into (InL>>(nbits-1-Amt))>>1, which is also valid since since we only need to care about Amt up nbits-1. It's hard to tell which one is better since the shift might be expensive if this stage of expansion is not yet a legal machine integer, whereas comparisons with zero are relatively cheap at all sizes, but more expensive than a shift if the shift is on a legal machine type. Patch by Keno Fischer! Test Plan: regression test from http://reviews.llvm.org/D7752 Reviewers: chfast, resistor Reviewed By: chfast, resistor Subscribers: sanjoy, resistor, chfast, llvm-commits Differential Revision: http://reviews.llvm.org/D4978 llvm-svn: 235370
22 lines
601 B
LLVM
22 lines
601 B
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s -check-prefix=CHECK-X64
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; RUN: llc < %s -march=x86-64 -O2 | FileCheck %s -check-prefix=CHECK-X64
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; CHECK-LABEL: shift1
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define void @shift1(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
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entry:
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%0 = ashr i256 %x, %a
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store i256 %0, i256* %r
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ret void
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}
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; CHECK-LABEL: shift2
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define i256 @shift2(i256 %c) nounwind
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{
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%b = shl i256 1, %c ; %c must not be a constant
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; Special case when %c is 0:
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; CHECK-X64: testb [[REG:%r[0-9]+b]], [[REG]]
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; CHECK-X64: cmoveq
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ret i256 %b
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}
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