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e86b7c773c
This patch allows targets to define multiple cost values for each register so that the cost model can be more flexible and better used during the register allocation as per the target requirements. For AMDGPU the VGPR allocation will be more efficient if the register cost can be associated dynamically based on the calling convention. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D86836
72 lines
2.6 KiB
TableGen
72 lines
2.6 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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// Checks the cost values for the register tuple.
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include "llvm/Target/Target.td"
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"MyTarget", types, size, registers> {
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let Size = size;
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}
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class Indexes<int N> {
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list<int> all = [0, 1, 2, 3];
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list<int> slice =
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!foldl([]<int>, all, acc, cur,
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!listconcat(acc, !if(!lt(cur, N), [cur], [])));
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}
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foreach Index = 0-3 in {
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def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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}
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foreach Size = {2,4} in {
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foreach Index = Indexes<!add(5, !mul(Size, -1))>.slice in {
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def !foldl("", Indexes<Size>.slice, acc, cur,
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!strconcat(acc#!if(!eq(acc,""),"","_"), "sub"#!add(cur, Index))) :
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SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
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let CoveringSubRegIndices =
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!foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
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!listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
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}
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}
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}
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let Namespace = "MyTarget" in {
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foreach Index = 0-15 in {
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// Adding two cost values per register.
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let CostPerUse = [Index, !shl(Index, 1)] in {
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def S#Index : Register <"s"#Index>;
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}
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}
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} // Namespace = "MyTarget"
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def GPR32 : MyClass<32, [i32], (sequence "S%u", 0, 15)>;
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def GPR64 : RegisterTuples<[sub0, sub1],
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[(decimate (shl GPR32, 0), 1),
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(decimate (shl GPR32, 1), 1)
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]>;
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def GPR128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[
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(decimate (shl GPR32, 0), 1),
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(decimate (shl GPR32, 1), 1),
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(decimate (shl GPR32, 2), 1),
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(decimate (shl GPR32, 3), 1)
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]>;
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def GPR_64 : MyClass<64, [v2i32], (add GPR64)>;
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def GPR_128 : MyClass<128, [v4i32], (add GPR128)>;
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def MyTarget : Target;
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// CHECK: static const uint8_t CostPerUseTable[] = {
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// CHECK-NEXT: 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, };
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// CHECK: static const TargetRegisterInfoDesc MyTargetRegInfoDesc = { // Extra Descriptors
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// CHECK-NEXT: CostPerUseTable, 2, InAllocatableClassTable};
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// CHECK: TargetRegisterInfo(&MyTargetRegInfoDesc, RegisterClasses, RegisterClasses+3,
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