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The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
31 lines
1.4 KiB
LLVM
31 lines
1.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone
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; SI-LABEL: {{^}}test_trig_preop_f64:
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; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]]
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; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
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; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
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; SI: buffer_store_dwordx2 [[RESULT]],
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; SI: s_endpgm
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define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%a = load double, double addrspace(1)* %aptr, align 8
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%b = load i32, i32 addrspace(1)* %bptr, align 4
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment:
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; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
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; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
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; SI: buffer_store_dwordx2 [[RESULT]],
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; SI: s_endpgm
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define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
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%a = load double, double addrspace(1)* %aptr, align 8
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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