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31 lines
905 B
LLVM
31 lines
905 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we are able to predicate instructions with gp-relative
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; addressing mode.
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; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##g{{[01]}})
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; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##g{{[01]}})
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@g0 = external global i32
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@g1 = common global i32 0, align 4
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define i32 @f0(i8 zeroext %a0, i8 zeroext %a1) #0 {
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b0:
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%v0 = icmp eq i8 %a0, %a1
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br i1 %v0, label %b2, label %b1
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b1: ; preds = %b0
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%v1 = load i32, i32* @g1, align 4
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br label %b3
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b2: ; preds = %b0
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%v2 = load i32, i32* @g0, align 4
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store i32 %v2, i32* @g1, align 4
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br label %b3
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b3: ; preds = %b2, %b1
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%v3 = phi i32 [ %v1, %b1 ], [ %v2, %b2 ]
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ret i32 %v3
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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