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94eef3fc13
branch in ARM v4 code, since it gets clobbered by the return address before it is used. Instead of adding a new register class containing all the GPRs except LR, just use the existing tGPR class. llvm-svn: 96360
37 lines
1.3 KiB
LLVM
37 lines
1.3 KiB
LLVM
; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
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; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
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; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
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; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
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@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
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declare void @g(i32, i32, i32, i32)
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define void @f() {
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; CHECKV4: mov lr, pc
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; CHECKV5: blx
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; CHECKELF: PLT
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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}
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define void @g.upgrd.1() {
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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ret void
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}
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define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
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; CHECKV4: m_231b
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; CHECKV4: bx r{{.*}}
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BB0:
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%5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
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%t35 = volatile load i32* %5 ; <i32> [#uses=1]
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%6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1]
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%7 = getelementptr i32** %6, i32 86 ; <i32**> [#uses=1]
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%8 = load i32** %7 ; <i32*> [#uses=1]
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%9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1]
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%10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1]
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ret i32* %10
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}
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