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76aeb9f378
Summary: Previously, it returned the GPR16MMRegClass for all instructions which was incorrect for instructions like lwsp/lwgp and unnecesarily restricted the permitted registers for instructions like lw32. This fixes quite a few of the -verify-machineinstrs errors reported in PR27458. I've only added -verify-machineinstrs to one test in this change since I understand there is a plan to enable the verifier by default. Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19873 llvm-svn: 268918
83 lines
2.8 KiB
C++
83 lines
2.8 KiB
C++
//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
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#include "Mips.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "MipsGenRegisterInfo.inc"
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namespace llvm {
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class MipsRegisterInfo : public MipsGenRegisterInfo {
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public:
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enum class MipsPtrClass {
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/// The default register class for integer values.
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Default = 0,
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/// The subset of registers permitted in certain microMIPS instructions
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/// such as lw16.
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GPR16MM = 1,
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/// The stack pointer only.
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StackPointer = 2,
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/// The global pointer only.
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GlobalPointer = 3,
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};
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MipsRegisterInfo();
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/// Get PIC indirect call register
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static unsigned getPICCallReg();
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/// Code Generation virtual methods...
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const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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static const uint32_t *getMips16RetHelperMask();
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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/// Stack Frame Processing Methods
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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// Stack realignment queries.
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bool canRealignStack(const MachineFunction &MF) const override;
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/// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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/// \brief Return GPR register class.
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virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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private:
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virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
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int FrameIndex, uint64_t StackSize,
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int64_t SPOffset) const = 0;
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};
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} // end namespace llvm
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#endif
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