Daniel Sanders 207417b373 [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting def's upwards. ... Summary: This prevents vreg260 and D7 from being merged in: %vreg260<def> = LDC1 ... JAL <ga:@sin>, <regmask ... list not containing D7 ...> %D7<def> = COPY %vreg260; ... Doing so is not valid because the JAL clobbers the D7. This fixes the almabench regression in the LLVM 3.7.0 release branch. Reviewers: MatzeB Subscribers: MatzeB, qcolombet, hans, llvm-commits Differential Revision: http://reviews.llvm.org/D11649 llvm-svn: 243745		2015-07-31 12:58:55 +00:00
..
Analysis	Rename hasCompatibleFunctionAttributes->areInlineCompatible based	2015-07-29 22:09:48 +00:00
AsmParser	[opaque pointers] Avoid the use of pointee types when parsing inline asm in IR	2015-07-27 23:32:19 +00:00
Bitcode	Reserve some constant values for the Swift calling convention.	2015-07-28 04:05:45 +00:00
CodeGen	[regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting def's upwards.	2015-07-31 12:58:55 +00:00
DebugInfo	[RuntimeDyld] Make LoadedObjectInfo::getLoadedSectionAddress take a SectionRef	2015-07-28 17:52:11 +00:00
ExecutionEngine	[MCJIT] Fix PR20656 by teaching MCJIT to honor ExecutionEngine's global mapping.	2015-07-29 23:12:33 +00:00
Fuzzer	[libFuzzer] trace switch statements and apply mutations based on the expected case values	2015-07-31 01:33:06 +00:00
IR	[opaque pointers] Remove use of PointerType::getElementType in favor of GEPOperator::getSourceElementType	2015-07-29 20:26:23 +00:00
IRReader
LibDriver	Add support for producing thin archives in llvm-lib.	2015-07-17 16:01:11 +00:00
LineEditor
Linker
LTO	Remove access to the DataLayout in the TargetMachine	2015-07-24 16:04:22 +00:00
MC	[llvm-mc] Add --no-warn flag with -W alias to disable outputting warnings while assembling.	2015-07-27 22:39:14 +00:00
Object	ELFYAML: Enable parsing of EM_AMDGPU	2015-07-31 01:15:15 +00:00
Option	Add an ArgList::AddAllArgs that accepts a vector of OptSpecifier.	2015-07-29 17:34:41 +00:00
Passes
ProfileData
Support	Add amdopencl environment to triple	2015-07-30 08:16:51 +00:00
TableGen	TableGen: Support folding casts from bits to int	2015-07-31 01:12:06 +00:00
Target	Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX	2015-07-31 05:09:47 +00:00
Transforms	[libFuzzer] trace switch statements and apply mutations based on the expected case values	2015-07-31 01:33:06 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile