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a4698bb735
There are a couple of bugs with the sc, scs, ll, lld instructions expanding:
1. On R6 these instruction pack immediate offset into a 9-bit field. Now
if an immediate exceeds 9-bits assembler does not perform expansion and
just rejects such instruction.
2. On 64-bit non-PIC code if an operand is a symbol assembler generates
incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16
relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones.
To solve these problems this patch:
- Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands
which require expansion. Probably later all `mem_simm9` operands will be
able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`.
- Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the
`mem_simm9_exp`. That allows to know operand size in the `processInstruction`
method and decide whether we need to expand instruction.
- Adds `expandMem9Inst` method to expand instructions with 9-bit memory
immediate operand. This method just load immediate into a "base"
register used by origibal instruction:
sc $2, 256($sp) => addiu $1, $sp, 256
sc $2, 0($1)
- Fix `expandMem16Inst` to support a correct set of relocations for
symbol loading in case of 64-bit non-PIC code.
ll $12, symbol => lui $12, 0
R_MIPS_HIGHEST symbol
daddiu $12, $12, 0
R_MIPS_HIGHER symbol
dsll $12, $12, 16
daddiu $12, $12, 0
R_MIPS_HI16 symbol
dsll $12, $12, 16
ll $12, 0($12)
R_MIPS_LO16 symbol
- Fix `expandMem16Inst` to unify handling of 3 and 4 operands
instructions.
- Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method.
Task for next patches - implement expanding for other instructions use
`mem_simm9` operand and other `mem_simm##` operands.
Differential Revision: https://reviews.llvm.org/D70648
407 lines
16 KiB
ArmAsm
407 lines
16 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips2 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS32
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# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS32
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# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r2 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS32
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# RUN: llvm-mc -filetype=obj -triple mipsn32 -mcpu=mips3 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPSN32
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# RUN: llvm-mc -filetype=obj -triple mipsn32 -mcpu=mips64r6 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPSN32R6
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# RUN: llvm-mc -filetype=obj -triple mips64 -mcpu=mips64 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS64
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# RUN: llvm-mc -filetype=obj -triple mips64 -mcpu=mips64r2 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS64
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# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r6 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS32R6
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# RUN: llvm-mc -filetype=obj -triple mips64 -mcpu=mips64r6 %s -o - \
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# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS64R6
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sc $2, 128($sp)
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# MIPS32: e3 a2 00 80 sc $2, 128($sp)
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# MIPS32R6: 7f a2 40 26 sc $2, 128($sp)
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# MIPSN32: e3 a2 00 80 sc $2, 128($sp)
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# MIPSN32R6: 7f a2 40 26 sc $2, 128($sp)
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# MIPS64: e3 a2 00 80 sc $2, 128($sp)
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# MIPS64R6: 7f a2 40 26 sc $2, 128($sp)
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sc $2, -128($sp)
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# MIPS32: e3 a2 ff 80 sc $2, -128($sp)
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# MIPS32R6: 7f a2 c0 26 sc $2, -128($sp)
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# MIPSN32: e3 a2 ff 80 sc $2, -128($sp)
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# MIPSN32R6: 7f a2 c0 26 sc $2, -128($sp)
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# MIPS64: e3 a2 ff 80 sc $2, -128($sp)
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# MIPS64R6: 7f a2 c0 26 sc $2, -128($sp)
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sc $2, 256($sp)
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# MIPS32: e3 a2 01 00 sc $2, 256($sp)
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# MIPS32R6: 27 a1 01 00 addiu $1, $sp, 256
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: e3 a2 01 00 sc $2, 256($sp)
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# MIPSN32R6: 27 a1 01 00 addiu $1, $sp, 256
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: e3 a2 01 00 sc $2, 256($sp)
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# MIPS64R6: 67 a1 01 00 daddiu $1, $sp, 256
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, -257($sp)
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# MIPS32: e3 a2 fe ff sc $2, -257($sp)
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# MIPS32R6: 27 a1 fe ff addiu $1, $sp, -257
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: e3 a2 fe ff sc $2, -257($sp)
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# MIPSN32R6: 27 a1 fe ff addiu $1, $sp, -257
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: e3 a2 fe ff sc $2, -257($sp)
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# MIPS64R6: 67 a1 fe ff daddiu $1, $sp, -257
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, 32767($sp)
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# MIPS32: e3 a2 7f ff sc $2, 32767($sp)
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# MIPS32R6: 27 a1 7f ff addiu $1, $sp, 32767
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: e3 a2 7f ff sc $2, 32767($sp)
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# MIPSN32R6: 27 a1 7f ff addiu $1, $sp, 32767
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: e3 a2 7f ff sc $2, 32767($sp)
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# MIPS64R6: 67 a1 7f ff daddiu $1, $sp, 32767
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, 32768($sp)
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# MIPS32: 3c 01 00 01 lui $1, 1
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# MIPS32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32-NEXT: e0 22 80 00 sc $2, -32768($1)
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# MIPS32R6: 34 01 80 00 ori $1, $zero, 32768
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# MIPS32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: 3c 01 00 01 lui $1, 1
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# MIPSN32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32-NEXT: e0 22 80 00 sc $2, -32768($1)
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# MIPSN32R6: 34 01 80 00 ori $1, $zero, 32768
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# MIPSN32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: 3c 01 00 01 lui $1, 1
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# MIPS64-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64-NEXT: e0 22 80 00 sc $2, -32768($1)
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# MIPS64R6: 34 01 80 00 ori $1, $zero, 32768
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# MIPS64R6-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, -32768($sp)
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# MIPS32: e3 a2 80 00 sc $2, -32768($sp)
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# MIPS32R6: 27 a1 80 00 addiu $1, $sp, -32768
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: e3 a2 80 00 sc $2, -32768($sp)
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# MIPSN32R6: 27 a1 80 00 addiu $1, $sp, -32768
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: e3 a2 80 00 sc $2, -32768($sp)
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# MIPS64R6: 67 a1 80 00 daddiu $1, $sp, -32768
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, -32769($sp)
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# MIPS32: 3c 01 ff ff lui $1, 65535
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# MIPS32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32-NEXT: e0 22 7f ff sc $2, 32767($1)
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# MIPS32R6: 3c 01 ff ff aui $1, $zero, 65535
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# MIPS32R6-NEXT: 34 21 7f ff ori $1, $1, 32767
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# MIPS32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: 3c 01 ff ff lui $1, 65535
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# MIPSN32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32-NEXT: e0 22 7f ff sc $2, 32767($1)
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# MIPSN32R6: 3c 01 ff ff aui $1, $zero, 65535
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# MIPSN32R6-NEXT: 34 21 7f ff ori $1, $1, 32767
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# MIPSN32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: 3c 01 ff ff lui $1, 65535
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# MIPS64-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64-NEXT: e0 22 7f ff sc $2, 32767($1)
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# MIPS64R6: 3c 01 ff ff aui $1, $zero, 65535
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# MIPS64R6-NEXT: 34 21 7f ff ori $1, $1, 32767
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# MIPS64R6-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, 655987($sp)
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# MIPS32: 3c 01 00 0a lui $1, 10
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# MIPS32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32-NEXT: e0 22 02 73 sc $2, 627($1)
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# MIPS32R6: 3c 01 00 0a aui $1, $zero, 10
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# MIPS32R6-NEXT: 34 21 02 73 ori $1, $1, 627
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# MIPS32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: 3c 01 00 0a lui $1, 10
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# MIPSN32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32-NEXT: e0 22 02 73 sc $2, 627($1)
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# MIPSN32R6: 3c 01 00 0a aui $1, $zero, 10
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# MIPSN32R6-NEXT: 34 21 02 73 ori $1, $1, 627
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# MIPSN32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: 3c 01 00 0a lui $1, 10
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# MIPS64-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64-NEXT: e0 22 02 73 sc $2, 627($1)
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# MIPS64R6: 3c 01 00 0a aui $1, $zero, 10
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# MIPS64R6-NEXT: 34 21 02 73 ori $1, $1, 627
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# MIPS64R6-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $2, -655987($sp)
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# MIPS32: 3c 01 ff f6 lui $1, 65526
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# MIPS32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32-NEXT: e0 22 fd 8d sc $2, -627($1)
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# MIPS32R6: 3c 01 ff f5 aui $1, $zero, 65525
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# MIPS32R6-NEXT: 34 21 fd 8d ori $1, $1, 64909
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# MIPS32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPS32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPSN32: 3c 01 ff f6 lui $1, 65526
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# MIPSN32-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32-NEXT: e0 22 fd 8d sc $2, -627($1)
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# MIPSN32R6: 3c 01 ff f5 aui $1, $zero, 65525
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# MIPSN32R6-NEXT: 34 21 fd 8d ori $1, $1, 64909
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# MIPSN32R6-NEXT: 00 3d 08 21 addu $1, $1, $sp
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# MIPSN32R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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# MIPS64: 3c 01 ff f6 lui $1, 65526
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# MIPS64-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64-NEXT: e0 22 fd 8d sc $2, -627($1)
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# MIPS64R6: 3c 01 ff f5 aui $1, $zero, 65525
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# MIPS64R6-NEXT: 34 21 fd 8d ori $1, $1, 64909
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# MIPS64R6-NEXT: 00 3d 08 2d daddu $1, $1, $sp
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# MIPS64R6-NEXT: 7c 22 00 26 sc $2, 0($1)
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sc $12, symbol
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# MIPS32: 3c 01 00 00 lui $1, 0
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# MIPS32-NEXT: R_MIPS_HI16 symbol
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# MIPS32-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPS32-NEXT: R_MIPS_LO16 symbol
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# MIPS32R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPS32R6-NEXT: R_MIPS_HI16 symbol
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# MIPS32R6-NEXT: 24 21 00 00 addiu $1, $1, 0
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# MIPS32R6-NEXT: R_MIPS_LO16 symbol
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# MIPS32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
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# MIPSN32: 3c 01 00 00 lui $1, 0
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# MIPSN32-NEXT: R_MIPS_HI16 symbol
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# MIPSN32-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPSN32-NEXT: R_MIPS_LO16 symbol
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# MIPSN32R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPSN32R6-NEXT: R_MIPS_HI16 symbol
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# MIPSN32R6-NEXT: 24 21 00 00 addiu $1, $1, 0
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# MIPSN32R6-NEXT: R_MIPS_LO16 symbol
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# MIPSN32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
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# MIPS64: 3c 01 00 00 lui $1, 0
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# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
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sc $12, symbol($3)
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# MIPS32: 3c 01 00 00 lui $1, 0
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# MIPS32-NEXT: R_MIPS_HI16 symbol
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# MIPS32-NEXT: 00 23 08 21 addu $1, $1, $3
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# MIPS32-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPS32-NEXT: R_MIPS_LO16 symbol
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# MIPS32R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPS32R6-NEXT: R_MIPS_HI16 symbol
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# MIPS32R6-NEXT: 24 21 00 00 addiu $1, $1, 0
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# MIPS32R6-NEXT: R_MIPS_LO16 symbol
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# MIPS32R6-NEXT: 00 23 08 21 addu $1, $1, $3
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# MIPS32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
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# MIPSN32: 3c 01 00 00 lui $1, 0
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# MIPSN32-NEXT: R_MIPS_HI16 symbol
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# MIPSN32-NEXT: 00 23 08 21 addu $1, $1, $3
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# MIPSN32-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPSN32-NEXT: R_MIPS_LO16 symbol
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# MIPSN32R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPSN32R6-NEXT: R_MIPS_HI16 symbol
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# MIPSN32R6-NEXT: 24 21 00 00 addiu $1, $1, 0
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# MIPSN32R6-NEXT: R_MIPS_LO16 symbol
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# MIPSN32R6-NEXT: 00 23 08 21 addu $1, $1, $3
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# MIPSN32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
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# MIPS64: 3c 01 00 00 lui $1, 0
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# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64-NEXT: 00 23 08 2d daddu $1, $1, $3
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# MIPS64-NEXT: e0 2c 00 00 sc $12, 0($1)
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# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6: 3c 01 00 00 aui $1, $zero, 0
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# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
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# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
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# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
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# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
|
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# MIPS64R6-NEXT: 00 23 08 2d daddu $1, $1, $3
|
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# MIPS64R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
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|
|
sc $12, symbol+8
|
|
# MIPS32: 3c 01 00 00 lui $1, 0
|
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# MIPS32-NEXT: R_MIPS_HI16 symbol
|
|
# MIPS32-NEXT: e0 2c 00 08 sc $12, 8($1)
|
|
# MIPS32-NEXT: R_MIPS_LO16 symbol
|
|
|
|
# MIPS32R6: 3c 01 00 00 aui $1, $zero, 0
|
|
# MIPS32R6-NEXT: R_MIPS_HI16 symbol
|
|
# MIPS32R6-NEXT: 24 21 00 08 addiu $1, $1, 8
|
|
# MIPS32R6-NEXT: R_MIPS_LO16 symbol
|
|
# MIPS32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPSN32: 3c 01 00 00 lui $1, 0
|
|
# MIPSN32-NEXT: R_MIPS_HI16 symbol+0x8
|
|
# MIPSN32-NEXT: e0 2c 00 00 sc $12, 0($1)
|
|
# MIPSN32-NEXT: R_MIPS_LO16 symbol+0x8
|
|
|
|
# MIPSN32R6: 3c 01 00 00 aui $1, $zero, 0
|
|
# MIPSN32R6-NEXT: R_MIPS_HI16 symbol+0x8
|
|
# MIPSN32R6-NEXT: 24 21 00 00 addiu $1, $1, 0
|
|
# MIPSN32R6-NEXT: R_MIPS_LO16 symbol+0x8
|
|
# MIPSN32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPS64: 3c 01 00 00 lui $1, 0
|
|
# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
|
|
# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
|
|
# MIPS64-NEXT: 64 21 00 00 daddiu $1, $1, 0
|
|
# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64-NEXT: 00 01 0c 38 dsll $1, $1, 16
|
|
# MIPS64-NEXT: e0 2c 00 00 sc $12, 0($1)
|
|
# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
|
|
# MIPS64R6: 3c 01 00 00 aui $1, $zero, 0
|
|
# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
|
|
# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
|
|
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
|
|
# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64R6-NEXT: 00 01 0c 38 dsll $1, $1, 16
|
|
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
|
|
# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
|
|
# MIPS64R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
.option pic2
|
|
|
|
sc $12, symbol
|
|
# MIPS32: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPS32-NEXT: R_MIPS_GOT16 symbol
|
|
# MIPS32-NEXT: e0 2c 00 00 sc $12, 0($1)
|
|
|
|
# MIPS32R6: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPS32R6-NEXT: R_MIPS_GOT16 symbol
|
|
# MIPS32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPSN32: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPSN32-NEXT: R_MIPS_GOT_DISP symbol
|
|
# MIPSN32-NEXT: e0 2c 00 00 sc $12, 0($1)
|
|
|
|
# MIPSN32R6: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPSN32R6-NEXT: R_MIPS_GOT_DISP symbol
|
|
# MIPSN32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPS64: df 81 00 00 ld $1, 0($gp)
|
|
# MIPS64-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
|
|
# MIPS64-NEXT: e0 2c 00 00 sc $12, 0($1)
|
|
|
|
# MIPS64R6: df 81 00 00 ld $1, 0($gp)
|
|
# MIPS64R6-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
|
|
# MIPS64R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
sc $12, symbol+8
|
|
# MIPS32: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPS32-NEXT: R_MIPS_GOT16 symbol
|
|
# MIPS32-NEXT: e0 2c 00 08 sc $12, 8($1)
|
|
|
|
# MIPS32R6: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPS32R6-NEXT: R_MIPS_GOT16 symbol
|
|
# MIPS32R6-NEXT: 24 21 00 08 addiu $1, $1, 8
|
|
# MIPS32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPSN32: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPSN32-NEXT: R_MIPS_GOT_DISP symbol
|
|
# MIPSN32-NEXT: e0 2c 00 08 sc $12, 8($1)
|
|
|
|
# MIPSN32R6: 8f 81 00 00 lw $1, 0($gp)
|
|
# MIPSN32R6-NEXT: R_MIPS_GOT_DISP symbol
|
|
# MIPSN32R6-NEXT: 24 21 00 08 addiu $1, $1, 8
|
|
# MIPSN32R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|
|
|
|
# MIPS64: df 81 00 00 ld $1, 0($gp)
|
|
# MIPS64-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
|
|
# MIPS64-NEXT: e0 2c 00 08 sc $12, 8($1)
|
|
|
|
# MIPS64R6: df 81 00 00 ld $1, 0($gp)
|
|
# MIPS64R6-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
|
|
# MIPS64R6-NEXT: 64 21 00 08 daddiu $1, $1, 8
|
|
# MIPS64R6-NEXT: 7c 2c 00 26 sc $12, 0($1)
|