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https://github.com/RPCS3/llvm-mirror.git
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d1a8bb697a
The vector reduction intrinsics started life as experimental ops, so backend support was lacking. As part of promoting them to 1st-class intrinsics, however, codegen support was added/improved: D58015 D90247 So I think it is safe to now remove this complication from IR. Note that we still have an IR-level codegen expansion pass for these as discussed in D95690. Removing that is another step in simplifying the logic. Also note that x86 was already unconditionally forming reductions in IR, so there should be no difference for x86. I spot checked a couple of the tests here by running them through opt+llc and did not see any asm diffs. If we do find functional differences for other targets, it should be possible to (at least temporarily) restore the shuffle IR with the ExpandReductions IR pass. Differential Revision: https://reviews.llvm.org/D96552
306 lines
14 KiB
LLVM
306 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -prefer-predicated-reduction-select -dce -instcombine -S | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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define i32 @reduction_sum_single(i32* noalias nocapture %A) {
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; CHECK-LABEL: @reduction_sum_single(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[TMP25:%.*]], %pred.load.continue6 ]
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; CHECK: [[TMP24:%.*]] = select <4 x i1> [[TMP0:%.*]], <4 x i32> [[TMP23:%.*]], <4 x i32> zeroinitializer
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; CHECK: [[TMP25]] = add <4 x i32> [[VEC_PHI]], [[TMP24]]
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; CHECK: middle.block:
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; CHECK: [[TMP27:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP25]])
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;
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entry:
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br label %.lr.ph
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.lr.ph: ; preds = %entry, %.lr.ph
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%indvars.iv = phi i32 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]
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%sum.02 = phi i32 [ %l7, %.lr.ph ], [ 0, %entry ]
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%l2 = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l3 = load i32, i32* %l2, align 4
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%l7 = add i32 %sum.02, %l3
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph
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%sum.0.lcssa = phi i32 [ %l7, %.lr.ph ]
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ret i32 %sum.0.lcssa
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}
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define i32 @reduction_sum(i32* noalias nocapture %A, i32* noalias nocapture %B) {
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; CHECK-LABEL: @reduction_sum(
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[TMP47:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP44:%.*]] = add <4 x i32> [[VEC_PHI]], [[VEC_IND:%.*]]
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; CHECK: [[TMP45:%.*]] = add <4 x i32> [[TMP44]], [[TMP23:%.*]]
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; CHECK: [[TMP46:%.*]] = add <4 x i32> [[TMP45]], [[TMP43:%.*]]
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; CHECK: [[TMP47]] = select <4 x i1> [[TMP3:%.*]], <4 x i32> [[TMP46]], <4 x i32> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP49:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP47]])
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;
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entry:
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br label %.lr.ph
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.lr.ph: ; preds = %entry, %.lr.ph
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%indvars.iv = phi i32 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]
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%sum.02 = phi i32 [ %l9, %.lr.ph ], [ 0, %entry ]
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%l2 = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l3 = load i32, i32* %l2, align 4
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%l4 = getelementptr inbounds i32, i32* %B, i32 %indvars.iv
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%l5 = load i32, i32* %l4, align 4
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%l7 = add i32 %sum.02, %indvars.iv
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%l8 = add i32 %l7, %l3
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%l9 = add i32 %l8, %l5
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph
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%sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]
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ret i32 %sum.0.lcssa
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}
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define i32 @reduction_prod(i32* noalias nocapture %A, i32* noalias nocapture %B) {
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; CHECK-LABEL: @reduction_prod(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 1, i32 1, i32 1, i32 1>, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP44:%.*]] = mul <4 x i32> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP45:%.*]] = mul <4 x i32> [[TMP44]], [[TMP43:%.*]]
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; CHECK: [[TMP46]] = select <4 x i1> [[TMP3:%.*]], <4 x i32> [[TMP45]], <4 x i32> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP46]])
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;
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entry:
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br label %.lr.ph
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.lr.ph: ; preds = %entry, %.lr.ph
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%indvars.iv = phi i32 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]
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%prod.02 = phi i32 [ %l9, %.lr.ph ], [ 1, %entry ]
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%l2 = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l3 = load i32, i32* %l2, align 4
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%l4 = getelementptr inbounds i32, i32* %B, i32 %indvars.iv
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%l5 = load i32, i32* %l4, align 4
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%l8 = mul i32 %prod.02, %l3
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%l9 = mul i32 %l8, %l5
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph
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%prod.0.lcssa = phi i32 [ %l9, %.lr.ph ]
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ret i32 %prod.0.lcssa
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}
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define i32 @reduction_and(i32* nocapture %A, i32* nocapture %B) {
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; CHECK-LABEL: @reduction_and(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 -1, i32 -1, i32 -1, i32 -1>, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP44:%.*]] = and <4 x i32> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP45:%.*]] = and <4 x i32> [[TMP44]], [[TMP43:%.*]]
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; CHECK: [[TMP46]] = select <4 x i1> [[TMP3:%.*]], <4 x i32> [[TMP45]], <4 x i32> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP46]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %and, %for.body ], [ -1, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l0 = load i32, i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %B, i32 %indvars.iv
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%l1 = load i32, i32* %arrayidx2, align 4
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%add = and i32 %result.08, %l0
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%and = and i32 %add, %l1
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ %and, %for.body ]
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ret i32 %result.0.lcssa
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}
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define i32 @reduction_or(i32* nocapture %A, i32* nocapture %B) {
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; CHECK-LABEL: @reduction_or(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP45:%.*]] = select <4 x i1> [[TMP3:%.*]], <4 x i32> [[TMP44:%.*]], <4 x i32> zeroinitializer
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; CHECK: [[TMP46]] = or <4 x i32> [[VEC_PHI]], [[TMP45]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP46]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %or, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l0 = load i32, i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %B, i32 %indvars.iv
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%l1 = load i32, i32* %arrayidx2, align 4
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%add = add nsw i32 %l1, %l0
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%or = or i32 %add, %result.08
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ %or, %for.body ]
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ret i32 %result.0.lcssa
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}
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define i32 @reduction_xor(i32* nocapture %A, i32* nocapture %B) {
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; CHECK-LABEL: @reduction_xor(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP45:%.*]] = select <4 x i1> [[TMP3:%.*]], <4 x i32> [[TMP44:%.*]], <4 x i32> zeroinitializer
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; CHECK: [[TMP46]] = xor <4 x i32> [[VEC_PHI]], [[TMP45]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP46]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %xor, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l0 = load i32, i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %B, i32 %indvars.iv
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%l1 = load i32, i32* %arrayidx2, align 4
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%add = add nsw i32 %l1, %l0
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%xor = xor i32 %add, %result.08
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ %xor, %for.body ]
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ret i32 %result.0.lcssa
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}
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define float @reduction_fadd(float* nocapture %A, float* nocapture %B) {
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; CHECK-LABEL: @reduction_fadd(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP44:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP45:%.*]] = fadd fast <4 x float> [[TMP44]], [[TMP43:%.*]]
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; CHECK: [[TMP46]] = select <4 x i1> [[TMP3:%.*]], <4 x float> [[TMP45]], <4 x float> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP46]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi float [ %fadd, %for.body ], [ 0.0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %A, i32 %indvars.iv
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%l0 = load float, float* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds float, float* %B, i32 %indvars.iv
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%l1 = load float, float* %arrayidx2, align 4
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%add = fadd fast float %result.08, %l0
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%fadd = fadd fast float %add, %l1
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi float [ %fadd, %for.body ]
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ret float %result.0.lcssa
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}
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define float @reduction_fmul(float* nocapture %A, float* nocapture %B) {
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; CHECK-LABEL: @reduction_fmul(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %vector.ph ], [ [[TMP46:%.*]], %pred.load.continue14 ]
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; CHECK: [[TMP44:%.*]] = fmul fast <4 x float> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP45:%.*]] = fmul fast <4 x float> [[TMP44]], [[TMP43:%.*]]
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; CHECK: [[TMP46]] = select <4 x i1> [[TMP3:%.*]], <4 x float> [[TMP45]], <4 x float> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP48:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[TMP46]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi float [ %fmul, %for.body ], [ 0.0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %A, i32 %indvars.iv
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%l0 = load float, float* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds float, float* %B, i32 %indvars.iv
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%l1 = load float, float* %arrayidx2, align 4
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%add = fmul fast float %result.08, %l0
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%fmul = fmul fast float %add, %l1
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi float [ %fmul, %for.body ]
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ret float %result.0.lcssa
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}
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define i32 @reduction_min(i32* nocapture %A, i32* nocapture %B) {
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; CHECK-LABEL: @reduction_min(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 1000, i32 1000, i32 1000, i32 1000>, %vector.ph ], [ [[TMP26:%.*]], %pred.load.continue6 ]
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; CHECK: [[TMP24:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP25:%.*]] = select <4 x i1> [[TMP24]], <4 x i32> [[VEC_PHI]], <4 x i32> [[TMP23]]
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; CHECK: [[TMP26]] = select <4 x i1> [[TMP0:%.*]], <4 x i32> [[TMP25]], <4 x i32> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP28:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP26]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l0 = load i32, i32* %arrayidx, align 4
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%c0 = icmp slt i32 %result.08, %l0
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%v0 = select i1 %c0, i32 %result.08, i32 %l0
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ %v0, %for.body ]
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ret i32 %result.0.lcssa
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}
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define i32 @reduction_max(i32* nocapture %A, i32* nocapture %B) {
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; CHECK-LABEL: @reduction_max(
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; CHECK: vector.body:
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; CHECK: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 1000, i32 1000, i32 1000, i32 1000>, %vector.ph ], [ [[TMP26:%.*]], %pred.load.continue6 ]
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; CHECK: [[TMP24:%.*]] = icmp ugt <4 x i32> [[VEC_PHI]], [[TMP23:%.*]]
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; CHECK: [[TMP25:%.*]] = select <4 x i1> [[TMP24]], <4 x i32> [[VEC_PHI]], <4 x i32> [[TMP23]]
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; CHECK: [[TMP26]] = select <4 x i1> [[TMP0:%.*]], <4 x i32> [[TMP25]], <4 x i32> [[VEC_PHI]]
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; CHECK: middle.block:
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; CHECK: [[TMP28:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP26]])
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
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%l0 = load i32, i32* %arrayidx, align 4
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%c0 = icmp ugt i32 %result.08, %l0
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%v0 = select i1 %c0, i32 %result.08, i32 %l0
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%indvars.iv.next = add i32 %indvars.iv, 1
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%exitcond = icmp eq i32 %indvars.iv.next, 257
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ %v0, %for.body ]
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ret i32 %result.0.lcssa
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}
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