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https://github.com/RPCS3/llvm-mirror.git
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9554f63212
Optimize leaf functions by not generating save/restore for callee saved registers. Update regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91539
188 lines
4.9 KiB
LLVM
188 lines
4.9 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define zeroext i1 @setccaf(float, float) {
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; CHECK-LABEL: setccaf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or %s0, 0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp false float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccat(float, float) {
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; CHECK-LABEL: setccat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or %s0, 1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp true float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccoeq(float, float) {
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; CHECK-LABEL: setccoeq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp oeq float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccone(float, float) {
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; CHECK-LABEL: setccone:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp one float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccogt(float, float) {
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; CHECK-LABEL: setccogt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ogt float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccoge(float, float) {
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; CHECK-LABEL: setccoge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp oge float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccolt(float, float) {
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; CHECK-LABEL: setccolt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp olt float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccole(float, float) {
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; CHECK-LABEL: setccole:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ole float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccord(float, float) {
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; CHECK-LABEL: setccord:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ord float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccuno(float, float) {
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; CHECK-LABEL: setccuno:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp uno float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccueq(float, float) {
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; CHECK-LABEL: setccueq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ueq float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccune(float, float) {
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; CHECK-LABEL: setccune:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp une float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccugt(float, float) {
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; CHECK-LABEL: setccugt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ugt float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccuge(float, float) {
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; CHECK-LABEL: setccuge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp uge float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccult(float, float) {
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; CHECK-LABEL: setccult:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ult float %0, %1
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ret i1 %3
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}
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define zeroext i1 @setccule(float, float) {
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; CHECK-LABEL: setccule:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = fcmp ule float %0, %1
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ret i1 %3
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}
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