Craig Topper ae70485f74 [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi. ... These instructions don't really exist, but we have ways we can emulate them. .vv will swap operands and use vmsle().vv. .vi will adjust the immediate and use .vmsgt(u).vi when possible. For .vx we need to use some of the multiple instruction sequences from the V extension spec. For unmasked vmsge(u).vx we use: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd For cases where mask and maskedoff are the same value then we have vmsge{u}.vx v0, va, x, v0.t which is the vd==v0 case that requires a temporary so we use: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt For other masked cases we use this sequence: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 We trust that register allocation will prevent vd in vmslt{u}.vx from being v0 since v0 is still needed by the vmxor. Differential Revision: https://reviews.llvm.org/D100925		2021-04-22 10:44:38 -07:00
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llvm	[RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi.	2021-04-22 10:44:38 -07:00
llvm-c	[LTO][Legacy] Decouple option parsing from LTOCodeGenerator	2021-03-31 16:43:26 +00:00