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llvm-mirror/test/TableGen/intrinsic-varargs.td
Tim Renouf dd05e6c883 [CodeGen] Defined MVTs v3i32, v3f32, v5i32, v5f32
AMDGPU would like to use these MVTs.

Differential Revision: https://reviews.llvm.org/D58901

Change-Id: I6125fea810d7cc62a4b4de3d9904255a1233ae4e
llvm-svn: 356351
2019-03-17 22:56:38 +00:00

33 lines
856 B
TableGen

// RUN: llvm-tblgen -gen-intrinsic-impl %s | FileCheck %s
// XFAIL: vg_leak
class IntrinsicProperty;
class SDNodeProperty;
class ValueType<int size, int value> {
string Namespace = "MVT";
int Size = size;
int Value = value;
}
class LLVMType<ValueType vt> {
ValueType VT = vt;
}
class Intrinsic<string name, list<LLVMType> param_types = []> {
string LLVMName = name;
bit isTarget = 0;
string TargetPrefix = "";
list<LLVMType> RetTypes = [];
list<LLVMType> ParamTypes = param_types;
list<IntrinsicProperty> IntrProperties = [];
list<SDNodeProperty> Properties = [];
}
// isVoid needs to match the definition in ValueTypes.td
def isVoid : ValueType<0, 115>; // Produces no value
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
// CHECK: /* 0 */ 0, 29, 0,
def int_foo : Intrinsic<"llvm.foo", [llvm_vararg_ty]>;