Daniel Sanders 2a30e4fcab [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. ... Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018		2014-06-16 13:13:03 +00:00
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CMakeLists.txt	Cleaning up a bunch of pre-Visual C++ 2012 build hacks.	2014-03-04 09:23:33 +00:00
LLVMBuild.txt	LLVMBuild.txt: Reformat.	2014-04-10 11:16:17 +00:00
Makefile	This is a resubmittal. For some reason it broke the bots yesterday	2013-01-19 02:00:40 +00:00
MipsDisassembler.cpp	[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.	2014-06-16 13:13:03 +00:00