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3f37fd8049
This reapplies commit r268796, with a fix for the setting of the inline asm constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the regular processing of the GR operands (setting of the subregisters) happens. Original commit log: [X86] Add a new LOW32_ADDR_ACCESS_RBP register class. ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. llvm-svn: 268955
35 lines
925 B
LLVM
35 lines
925 B
LLVM
; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
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; x32 uses %esp, %ebp as stack and frame pointers
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; CHECK-LABEL: foo
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: movq %rdi, -8(%rbp)
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; CHECK: popq %rbp
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; X32ABI-LABEL: foo
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; X32ABI: pushq %rbp
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; X32ABI: movl %esp, %ebp
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; X32ABI: movl %edi, -4(%ebp)
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; X32ABI: popq %rbp
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; NACL-LABEL: foo
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; NACL: pushq %rbp
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; NACL: movq %rsp, %rbp
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; NACL: movl %edi, -4(%rbp)
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; NACL: popq %rbp
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define void @foo(i32* %a) #0 {
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entry:
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%a.addr = alloca i32*, align 4
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%b = alloca i32*, align 4
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store i32* %a, i32** %a.addr, align 4
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ret void
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}
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attributes #0 = { nounwind uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
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