Matt Arsenault 21aca8a3e2 GlobalISel: Reduce G_SHL width if source is extension ... shl ([sza]ext x, y) => zext (shl x, y). Turns expensive 64 bit shifts into 32 bit if it does not overflow the source type: This is a port of an AMDGPU DAG combine added in 5fa289f0d8ff85b9e14d2f814a90761378ab54ae. InstCombine does this already, but we need to do it again here to apply it to shifts introduced for lowered getelementptrs. This will help matching addressing modes that use 32-bit offsets in a future patch. TableGen annoyingly assumes only a single match data operand, so introduce a reusable struct. However, this still requires defining a separate GIMatchData for every combine which is still annoying. Adds a morally equivalent function to the existing getShiftAmountTy. Without this, we would have to do try to repeatedly query the legalizer info and guess at what type to use for the shift.		2020-08-24 09:42:40 -04:00
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llvm	GlobalISel: Reduce G_SHL width if source is extension	2020-08-24 09:42:40 -04:00
llvm-c	[DebugInfo][flang]Added support for representing Fortran assumed length strings	2020-08-22 10:13:40 +05:30