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llvm-mirror/test/CodeGen/ARM/tst-peephole.mir
Eli Friedman e8f47359b8 [ARM] Don't form "ands" when it isn't scheduled correctly.
In r322972/r323136, the iteration here was changed to catch cases at the
beginning of a basic block... but we accidentally deleted an important
safety check.  Restore that check to the way it was.

Fixes https://bugs.llvm.org/show_bug.cgi?id=41116

Differential Revision: https://reviews.llvm.org/D59680

llvm-svn: 356809
2019-03-22 20:49:15 +00:00

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# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
# The and -> ands transform is sensitive to scheduling; make sure we don't
# transform cases which aren't legal.
# CHECK-LABEL: name: foo_transform
# CHECK: %2:gpr = ANDri %0, 1, 14, $noreg, def $cpsr
# CHECK-NEXT: %3:gpr = MOVCCi16 %1, 5, 0, $cpsr
# CHECK-LABEL: name: foo_notransform
# CHECK: TSTri %0, 1, 14, $noreg, implicit-def $cpsr
# CHECK-NEXT: %2:gpr = MOVCCi16 %1, 5, 0, $cpsr
--- |
target triple = "armv7-unknown-unknown"
define i32 @foo_transform(i32 %in) {
ret i32 undef
}
define i32 @foo_notransform(i32 %in) {
ret i32 undef
}
...
---
name: foo_transform
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
liveins: $r0
%1:gpr = COPY $r0
%2:gpr = MOVi 4, 14, $noreg, $noreg
%4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
%3:gpr = MOVCCi16 %2, 5, 0, $cpsr
$r0 = COPY killed %3
$r1 = COPY killed %4
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
name: foo_notransform
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
liveins: $r0
%1:gpr = COPY $r0
%2:gpr = MOVi 4, 14, $noreg, $noreg
TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
%3:gpr = MOVCCi16 %2, 5, 0, $cpsr
%4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
$r0 = COPY killed %3
$r1 = COPY killed %4
BX_RET 14, $noreg, implicit $r0, implicit $r1