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fa4a9158e9
This is a follow-up to the FIXME that was added with D7474 ( http://reviews.llvm.org/rL229531 ). I thought this load folding bug had been made hard-to-hit, but it turns out to be very easy when targeting 32-bit x86 and causes a miscompile/crash in Wine: https://bugs.winehq.org/show_bug.cgi?id=38826 https://llvm.org/bugs/show_bug.cgi?id=22371#c25 The quick fix is to simply remove the scalar FP logical instructions from the load folding table in X86InstrInfo, but that causes us to miss load folds that should be possible when lowering fabs, fneg, fcopysign. So the majority of this patch is altering those lowerings to use *vector* FP logical instructions (because that's all x86 gives us anyway). That lets us do the load folding legally. Differential Revision: http://reviews.llvm.org/D11477 llvm-svn: 243361
76 lines
2.3 KiB
LLVM
76 lines
2.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
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define <2 x double> @fabs_v2f64(<2 x double> %p)
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{
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; CHECK-LABEL: fabs_v2f64
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; CHECK: vandpd
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%t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
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define <4 x float> @fabs_v4f32(<4 x float> %p)
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{
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; CHECK-LABEL: fabs_v4f32
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; CHECK: vandps
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%t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
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ret <4 x float> %t
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
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define <4 x double> @fabs_v4f64(<4 x double> %p)
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{
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; CHECK-LABEL: fabs_v4f64
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; CHECK: vandpd
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%t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
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define <8 x float> @fabs_v8f32(<8 x float> %p)
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{
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; CHECK-LABEL: fabs_v8f32
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; CHECK: vandps
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%t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
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ret <8 x float> %t
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}
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declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
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; PR20354: when generating code for a vector fabs op,
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; make sure that we're only turning off the sign bit of each float value.
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; No constant pool loads or vector ops are needed for the fabs of a
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; bitcasted integer constant; we should just return an integer constant
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; that has the sign bits turned off.
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;
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; So instead of something like this:
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; movabsq (constant pool load of mask for sign bits)
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; vmovq (move from integer register to vector/fp register)
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; vandps (mask off sign bits)
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; vmovq (move vector/fp register back to integer return register)
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;
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; We should generate:
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; mov (put constant value in return register)
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define i64 @fabs_v2f32_1() {
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; CHECK-LABEL: fabs_v2f32_1:
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; CHECK: movabsq $9223372032559808512, %rax # imm = 0x7FFFFFFF00000000
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; CHECK-NEXT: retq
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%bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
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%ret = bitcast <2 x float> %fabs to i64
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ret i64 %ret
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}
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define i64 @fabs_v2f32_2() {
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; CHECK-LABEL: fabs_v2f32_2:
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; CHECK: movl $2147483647, %eax # imm = 0x7FFFFFFF
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; CHECK-NEXT: retq
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%bitcast = bitcast i64 4294967295 to <2 x float> ; 0x0000_0000_FFFF_FFFF
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
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%ret = bitcast <2 x float> %fabs to i64
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ret i64 %ret
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}
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declare <2 x float> @llvm.fabs.v2f32(<2 x float> %p)
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