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66 lines
2.3 KiB
C++
66 lines
2.3 KiB
C++
//===---------------------------- Context.cpp -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages.
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///
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//===----------------------------------------------------------------------===//
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#include "Context.h"
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#include "DispatchStage.h"
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#include "ExecuteStage.h"
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#include "FetchStage.h"
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#include "RegisterFile.h"
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#include "RetireControlUnit.h"
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#include "RetireStage.h"
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#include "Scheduler.h"
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namespace mca {
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using namespace llvm;
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std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
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SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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// Create the hardware units defining the backend.
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auto RCU = llvm::make_unique<RetireControlUnit>(SM);
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auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto LSU = llvm::make_unique<LSUnit>(Opts.LoadQueueSize, Opts.StoreQueueSize,
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Opts.AssumeNoAlias);
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auto HWS = llvm::make_unique<Scheduler>(SM, LSU.get());
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// Create the pipeline and its stages.
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auto StagePipeline = llvm::make_unique<Pipeline>();
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auto Fetch = llvm::make_unique<FetchStage>(IB, SrcMgr);
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auto Dispatch = llvm::make_unique<DispatchStage>(
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STI, MRI, Opts.RegisterFileSize, Opts.DispatchWidth, *RCU, *PRF);
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auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
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auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
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// Pass the ownership of all the hardware units to this Context.
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addHardwareUnit(std::move(RCU));
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addHardwareUnit(std::move(PRF));
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addHardwareUnit(std::move(LSU));
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addHardwareUnit(std::move(HWS));
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// Build the pipeline.
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StagePipeline->appendStage(std::move(Fetch));
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StagePipeline->appendStage(std::move(Dispatch));
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StagePipeline->appendStage(std::move(Execute));
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StagePipeline->appendStage(std::move(Retire));
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return StagePipeline;
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}
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} // namespace mca
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