mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 20:12:56 +02:00
bd51d0c9b1
Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse,+soft-float \
|
|
; RUN: | FileCheck %s --check-prefix=SOFT1 --check-prefix=CHECK
|
|
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2,+soft-float \
|
|
; RUN: | FileCheck %s --check-prefix=SOFT2 --check-prefix=CHECK
|
|
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse \
|
|
; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK
|
|
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 \
|
|
; RUN: | FileCheck %s --check-prefix=SSE2 --check-prefix=CHECK
|
|
; RUN: llc < %s -mtriple=x86_64-gnux32 -mattr=+mmx,+sse2,+soft-float | FileCheck %s
|
|
|
|
; CHECK-NOT: xmm{{[0-9]+}}
|
|
|
|
%struct.__va_list_tag = type { i32, i32, i8*, i8* }
|
|
|
|
define i32 @t1(i32 %a, ...) nounwind {
|
|
entry:
|
|
%va = alloca [1 x %struct.__va_list_tag], align 8 ; <[1 x %struct.__va_list_tag]*> [#uses=2]
|
|
%va12 = bitcast [1 x %struct.__va_list_tag]* %va to i8* ; <i8*> [#uses=2]
|
|
call void @llvm.va_start(i8* %va12)
|
|
%va3 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
|
|
call void @bar(%struct.__va_list_tag* %va3) nounwind
|
|
call void @llvm.va_end(i8* %va12)
|
|
ret i32 undef
|
|
; CHECK-LABEL: t1:
|
|
; CHECK: ret{{[lq]}}
|
|
}
|
|
|
|
declare void @llvm.va_start(i8*) nounwind
|
|
|
|
declare void @bar(%struct.__va_list_tag*)
|
|
|
|
declare void @llvm.va_end(i8*) nounwind
|
|
|
|
define float @t2(float %a, float %b) nounwind readnone {
|
|
entry:
|
|
%0 = fadd float %a, %b ; <float> [#uses=1]
|
|
ret float %0
|
|
; CHECK-LABEL: t2:
|
|
; SOFT1-NOT: xmm{{[0-9]+}}
|
|
; SOFT2-NOT: xmm{{[0-9]+}}
|
|
; SSE1: xmm{{[0-9]+}}
|
|
; SSE2: xmm{{[0-9]+}}
|
|
; CHECK: ret{{[lq]}}
|
|
}
|
|
|
|
; soft-float means no SSE instruction and passing fp128 as pair of i64.
|
|
define fp128 @t3(fp128 %a, fp128 %b) nounwind readnone {
|
|
entry:
|
|
%0 = fadd fp128 %b, %a
|
|
ret fp128 %0
|
|
; CHECK-LABEL: t3:
|
|
; SOFT1-NOT: xmm{{[0-9]+}}
|
|
; SOFT2-NOT: xmm{{[0-9]+}}
|
|
; SSE1: xmm{{[0-9]+}}
|
|
; SSE2: xmm{{[0-9]+}}
|
|
; CHECK: ret{{[lq]}}
|
|
}
|