Matt Arsenault 22a9f67443 Implement new way of expanding extloads. ... Now that the source and destination types can be specified, allow doing an expansion that doesn't use an EXTLOAD of the result type. Try to do a legal extload to an intermediate type and extend that if possible. This generalizes the special case custom lowering of extloads R600 has been using to work around this problem. This also happens to fix a bug that would incorrectly use more aligned loads than should be used. llvm-svn: 225925		2015-01-14 01:35:17 +00:00
..
AArch64	Fix PR22179.	2015-01-10 23:41:24 +00:00
ARM	Debug info: Factor out the creation of DWARF expressions from AsmPrinter	2015-01-12 22:19:22 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
Inputs
Mips	Insert random noops to increase security against ROP attacks (llvm)	2015-01-14 01:07:26 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	Revert "r225811 - Revert "r225808 - [PowerPC] Add StackMap/PatchPoint support""	2015-01-14 01:07:51 +00:00
R600	Implement new way of expanding extloads.	2015-01-14 01:35:17 +00:00
SPARC
SystemZ	Use the integrated assembler as default on SystemZ	2015-01-13 19:45:16 +00:00
Thumb
Thumb2	[ARM] Fix a bug in constant island pass that was triggering an assertion.	2015-01-08 20:44:50 +00:00
X86	Insert random noops to increase security against ROP attacks (llvm)	2015-01-14 01:07:26 +00:00
XCore