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06b441af25
All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
93 lines
3.9 KiB
Plaintext
93 lines
3.9 KiB
Plaintext
MIPS Relocation Principles
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In LLVM, there are several elements of the llvm::ISD::NodeType enum
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that deal with addresses and/or relocations. These are defined in
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include/llvm/Target/TargetSelectionDAG.td, namely:
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GlobalAddress, GlobalTLSAddress, JumpTable, ConstantPool,
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ExternalSymbol, BlockAddress
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The MIPS backend uses several principles to handle these.
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1. Code for lowering addresses references to machine dependent code is
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factored into common code for generating different address forms and
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is called by the relocation model specific lowering function, using
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templated functions. For example:
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// lib/Target/Mips/MipsISelLowering.cpp
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SDValue MipsTargetLowering::
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lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
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calls
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template <class NodeTy> // lib/Target/Mips/MipsISelLowering.h
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SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty,
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SelectionDAG &DAG, bool IsN32OrN64) const
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which calls the overloaded function:
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// lib/Target/Mips/MipsISelLowering.h
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SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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2. Generic address nodes are lowered to some combination of target
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independent and machine specific SDNodes (for example:
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MipsISD::{Highest, Higher, Hi, Lo}) depending upon relocation model,
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ABI, and compilation options.
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The choice of specific instructions that are to be used is delegated
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to ISel which in turn relies on TableGen patterns to choose subtarget
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specific instructions. For example, in getAddrLocal, the pseudo-code
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generated is:
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(add (load (wrapper $gp, %got(sym)), %lo(sym))
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where "%lo" represents an instance of an SDNode with opcode
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"MipsISD::Lo", "wrapper" indicates one with opcode "MipsISD::Wrapper",
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and "%got" the global table pointer "getGlobalReg(...)". The "add" is
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"ISD::ADD", not a target dependent one.
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3. A TableGen multiclass pattern "MipsHiLoRelocs" is used to define a
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template pattern parameterized over the load upper immediate
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instruction, add operation, the zero register, and register class.
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Here the instantiation of MipsHiLoRelocs in MipsInstrInfo.td is used
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to MIPS32 to compute addresses for the static relocation model.
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// lib/Target/Mips/MipsInstrInfo.td
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multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
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Register ZeroReg, RegisterOperand GPROpnd> {
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def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>;
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...
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def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
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...
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def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaladdr:$lo)),
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(Addiu GPROpnd:$hi, tglobaladdr:$lo)>;
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...
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}
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defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
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// lib/Target/Mips/Mips64InstrInfo.td
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defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32;
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The instantiation in Mips64InstrInfo.td is used for MIPS64 in ILP32
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mode, as guarded by the predicate "SYM_32" and also for a submode of
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LP64 where symbols are assumed to be 32 bits wide.
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More details on how multiclasses in TableGen work can be found in the
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section "Multiclass definitions and instances" in the document
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"TableGen Language Introduction"
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4. Instruction definitions are multiply defined to cover the different
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register classes. In some cases, such as LW/LW64, this also accounts
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for the difference in the results of instruction execution. On MIPS32,
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"lw" loads a 32 bit value from memory. On MIPS64, "lw" loads a 32 bit
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value from memory and sign extends the value to 64 bits.
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// lib/Target/Mips/MipsInstrInfo.td
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def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
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// lib/Target/Mips/Mips64InstrInfo.td
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM;
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defines two names "LUi" and "LUi64" with two different register
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classes, but with the same encoding---"LUI_FM". These instructions load a
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16-bit immediate into bits 31-16 and clear the lower 15 bits. On MIPS64,
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the result is sign-extended to 64 bits.
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