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4ca961430f
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB llvm-svn: 156196
25 lines
785 B
LLVM
25 lines
785 B
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
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define ptx_device float @test_mul_add_f(float %x, float %y, float %z) {
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entry:
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; FMA: fma.rn.f32
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; MUL: mul.rn.f32
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; MUL: add.rn.f32
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%a = fmul float %x, %y
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%b = fadd float %a, %z
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ret float %b
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}
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define ptx_device double @test_mul_add_d(double %x, double %y, double %z) {
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entry:
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; FMA: fma.rn.f64
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; MUL: mul.rn.f64
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; MUL: add.rn.f64
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%a = fmul double %x, %y
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%b = fadd double %a, %z
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ret double %b
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}
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