1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/TableGen
Hans Wennborg 230a0cd001 Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
This broke the Chromium build, causing it to fail with e.g.

  fatal error: error in backend: Cannot select: t362: v4i32 = X86ISD::VSHLI t392, Constant:i8<15>

See llvm-commits thread of r372285 for details.

This also reverts r372286, r372287, r372288, r372289, r372290, r372291,
r372292, r372293, r372296, and r372297, which seemed to depend on the
main commit.

> Encode them directly as an imm argument to G_INTRINSIC*.
>
> Since now intrinsics can now define what parameters are required to be
> immediates, avoid using registers for them. Intrinsics could
> potentially want a constant that isn't a legal register type. Also,
> since G_CONSTANT is subject to CSE and legalization, transforms could
> potentially obscure the value (and create extra work for the
> selector). The register bank of a G_CONSTANT is also meaningful, so
> this could throw off future folding and legalization logic for AMDGPU.
>
> This will be much more convenient to work with than needing to call
> getConstantVRegVal and checking if it may have failed for every
> constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth
> immarg operands, many of which need inspection during lowering. Having
> to find the value in a register is going to add a lot of boilerplate
> and waste compile time.
>
> SelectionDAG has always provided TargetConstant for constants which
> should not be legalized or materialized in a register. The distinction
> between Constant and TargetConstant was somewhat fuzzy, and there was
> no automatic way to force usage of TargetConstant for certain
> intrinsic parameters. They were both ultimately ConstantSDNode, and it
> was inconsistently used. It was quite easy to mis-select an
> instruction requiring an immediate. For SelectionDAG, start emitting
> TargetConstant for these arguments, and using timm to match them.
>
> Most of the work here is to cleanup target handling of constants. Some
> targets process intrinsics through intermediate custom nodes, which
> need to preserve TargetConstant usage to match the intrinsic
> expectation. Pattern inputs now need to distinguish whether a constant
> is merely compatible with an operand or whether it is mandatory.
>
> The GlobalISelEmitter needs to treat timm as a special case of a leaf
> node, simlar to MachineBasicBlock operands. This should also enable
> handling of patterns for some G_* instructions with immediates, like
> G_FENCE or G_EXTRACT.
>
> This does include a workaround for a crash in GlobalISelEmitter when
> ARM tries to uses "imm" in an output with a "timm" pattern source.

llvm-svn: 372314
2019-09-19 12:33:07 +00:00
..
Common GlobalISel/TableGen: Handle setcc patterns 2019-08-29 01:13:41 +00:00
FixedLenDecoderEmitter [TableGen] Correct the shift to the proper bit width. 2019-08-10 16:15:06 +00:00
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
address-space-patfrags.td [GlobalISel] Check LLT size matches memory size for non-truncating stores. 2019-08-02 23:33:13 +00:00
AllowDuplicateRegisterNames.td
ambiguous-composition.td
AnonDefinitionOnDemand.td
arithmetic.td
AsmPredicateCondsEmission.td
AsmVariant.td
BigEncoder.td Fix compile-time regression caused by rL371928 2019-09-18 18:14:42 +00:00
BitOffsetDecoder.td
BitsInit.td
BitsInitOverflow.td
cast-list-initializer.td
cast-multiclass.td
cast-typeerror.td
cast.td
ClassInstanceValue.td
code.td
compare.td
ConcatenatedSubregs.td
cond-bitlist.td
cond-default.td
cond-empty-list-arg.td
cond-inheritance.td
cond-let.td
cond-list.td
cond-subclass.td
cond-type.td
cond-usage.td
condsbit.td
ConstraintChecking1.td
ConstraintChecking2.td
ConstraintChecking3.td
ConstraintChecking4.td
ConstraintChecking5.td
ConstraintChecking6.td
ConstraintChecking7.td
ConstraintChecking.inc
CStyleComment.td
dag-functional.td
dag-isel-res-order.td
Dag.td
DAGDefaultOps.td [TableGen] Allow DAG isel patterns to override default operands. 2019-07-04 08:43:20 +00:00
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
defset-typeerror.td
defset.td
DuplicateFieldValues.td
eq.td
eqbit.td
FastISelEmitter.td
FieldAccess.td
foldl.td
foreach-eval.td
foreach-leak.td
foreach-multiclass.td
foreach-range-parse-errors0.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-range-parse-errors1.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-range-parse-errors2.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-range-parse-errors3.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-range-parse-errors4.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-range-parse-errors5.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach-variable-range.td TableGen: Handle nontrivial foreach range bounds 2019-05-22 21:28:20 +00:00
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
generic-tables-instruction.td Update tablegen test after r369847. 2019-08-24 15:11:41 +00:00
generic-tables.td Update tablegen test after r369847. 2019-08-24 15:11:41 +00:00
get-operand-type.td [TableGen] Generate offsets into a flat array for getOperandType 2019-07-16 22:39:18 +00:00
gisel-physreg-input.td GlobalISel: Support physical register inputs in patterns 2019-09-06 20:32:37 +00:00
GlobalISelEmitter-PR39045.td [GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests 2019-08-13 22:14:37 +00:00
GlobalISelEmitter-setcc.td GlobalISel/TableGen: Handle setcc patterns 2019-08-29 01:13:41 +00:00
GlobalISelEmitter.td Use a bit of relaxed constexpr to make FeatureBitset costant intializable 2019-08-24 15:02:44 +00:00
GlobalISelEmitterOverloadedPtr.td Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands 2019-08-20 22:04:10 +00:00
GlobalISelEmitterRegSequence.td GlobalISel/TableGen: Handle REG_SEQUENCE patterns 2019-09-10 17:57:33 +00:00
GlobalISelEmitterSkippedPatterns.td [GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests 2019-08-13 22:14:37 +00:00
GlobalISelEmitterSubreg.td GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints 2019-09-06 00:05:58 +00:00
HwModeSelect.td
if-empty-list-arg.td
if-type.td
if.td
ifbit.td
Include.inc
Include.td
IntBitInit.td
intrin-side-effects.td [TableGen] Do not set ReadNone attribute on intrinsics with side effects 2019-07-17 10:53:13 +00:00
intrinsic-long-name.td
intrinsic-pointer-to-any.td Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty> 2019-06-26 00:08:22 +00:00
intrinsic-struct.td
intrinsic-varargs.td [TableGen] Include ValueTypes.td directly into the intrinsic-varargs.td test. 2019-08-21 19:14:38 +00:00
IntSpecialValues.td [TableGen] Allow 2^63-1 and 2^63-2 as int literals. 2019-03-12 09:28:19 +00:00
isa.td
JSON-check.py
JSON.td
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td [TableGen] Let list elements have a trailing comma 2019-03-26 11:16:01 +00:00
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
listpaste.td TableGen: Allow lists to be concatenated through '#' 2019-03-05 17:16:07 +00:00
ListSlices.td
listsplat.td [TableGen] Introduce !listsplat 'binary' operator 2019-04-10 18:26:36 +00:00
lit.local.cfg Attempt to fix issue with unresolved lit test in TableGen 2019-08-13 22:32:26 +00:00
LoLoL.td
math.td [Tablegen] Add support for the !mul operator. 2019-03-01 09:46:29 +00:00
MultiClass-def-fail.td [TableGen] Give meaningful msg for def use in multiclass 2019-03-26 10:49:09 +00:00
MultiClass-defm-fail.td
MultiClass-defm.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
name-resolution-consistency.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
prep-diag1.td
prep-diag2.td
prep-diag3.td
prep-diag4.td
prep-diag5.td TableGen: support #ifndef in addition to #ifdef. 2019-05-14 13:04:25 +00:00
prep-diag6.td
prep-diag7.td
prep-diag8.td
prep-diag9.td
prep-diag10.td
prep-diag11-include.inc
prep-diag11.td
prep-diag12-include.inc
prep-diag12.td
prep-diag13.td
prep-diag14.td
prep-ifndef-diag-1.td TableGen: support #ifndef in addition to #ifdef. 2019-05-14 13:04:25 +00:00
prep-ifndef-diag-2.td TableGen: support #ifndef in addition to #ifdef. 2019-05-14 13:04:25 +00:00
prep-ifndef.td TableGen: support #ifndef in addition to #ifdef. 2019-05-14 13:04:25 +00:00
prep-region-include.inc
prep-region-processing.td
RegisterBankEmitter.td
RegisterEncoder.td [CodeEmitter] Support instruction widths > 64 bits 2019-09-15 08:35:08 +00:00
RelTest.td
SchedModelError.td [TableGen] Include schedule model name in diagnostic. 2019-04-15 10:06:26 +00:00
searchabletables-intrinsic.td
self-reference-recursion.td
self-reference-typeerror.td
self-reference.td
SetTheory.td
SiblingForeach.td
size.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
template-arg-dependency.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td
trydecode-emission3.td
trydecode-emission.td
TwoLevelName.td
UnsetBitInit.td
unterminated-c-comment-include.inc
unterminated-c-comment.td
unterminated-code-block-include.inc
unterminated-code-block.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td