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a8e180d21c
This is needed for D74873, AMDGPU going to have 16 bit subregs and the largest tuple is 32 VGPRs, which results in 64 lanes. Differential Revision: https://reviews.llvm.org/D75378
24 lines
403 B
YAML
24 lines
403 B
YAML
# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
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# Check that the MIR parser can parse lane masks in block liveins.
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# CHECK-LABEL: name: foo
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# CHECK: bb.0:
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# CHECK: liveins: $d0:0x0000000000000002, $d1, $d2:0x0000000000000010
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--- |
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define void @foo() {
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ret void
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}
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0:0x00002, $d1, $d2:16
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A2_nop
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...
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