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Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
148 lines
6.1 KiB
TableGen
148 lines
6.1 KiB
TableGen
//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the 3DNow! instruction set, which extends MMX to support
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// floating point and also adds a few more random instructions for good measure.
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//
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//===----------------------------------------------------------------------===//
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let Sched = WriteFAdd in {
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def I3DNOW_FALU_ITINS : OpndItins<
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IIC_3DNOW_FALU_RR, IIC_3DNOW_FALU_RM
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>;
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}
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let Sched = WriteCvtF2I in {
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def I3DNOW_FCVT_F2I_ITINS : OpndItins<
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IIC_3DNOW_FCVT_F2I_RR, IIC_3DNOW_FCVT_F2I_RM
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>;
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}
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let Sched = WriteCvtI2F in {
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def I3DNOW_FCVT_I2F_ITINS : OpndItins<
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IIC_3DNOW_FCVT_I2F_RR, IIC_3DNOW_FCVT_I2F_RM
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>;
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}
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let Sched = WriteVecIMul in {
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def I3DNOW_MISC_FUNC_ITINS : OpndItins<
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IIC_3DNOW_MISC_FUNC_REG, IIC_3DNOW_MISC_FUNC_MEM
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>;
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}
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let Sched = WriteShuffle in {
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def I3DNOW_PSHUF_ITINS : OpndItins<
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IIC_MMX_PSHUF, IIC_MMX_PSHUF
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>;
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}
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class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
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InstrItinClass itin>
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: I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
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}
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class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
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InstrItinClass itin>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat, itin>,
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Has3DNow0F0FOpcode {
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let Constraints = "$src1 = $dst";
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}
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class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
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InstrItinClass itin>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat, itin>,
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Has3DNow0F0FOpcode;
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multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, OpndItins itins,
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bit Commutable = 0, string Ver = ""> {
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let isCommutable = Commutable in
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))],
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itins.rr>, Sched<[itins.Sched]>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, OpndItins itins,
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string Ver = ""> {
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def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))], itins.rr>,
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Sched<[itins.Sched]>;
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def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn))
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(bitconvert (load_mmx addr:$src))))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", I3DNOW_MISC_FUNC_ITINS, 1>;
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defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", I3DNOW_FCVT_F2I_ITINS>;
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defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", I3DNOW_FALU_ITINS>;
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defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", I3DNOW_FALU_ITINS, 1>;
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defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", I3DNOW_FALU_ITINS, 1>;
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defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", I3DNOW_FALU_ITINS>;
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defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", I3DNOW_FALU_ITINS>;
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defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", I3DNOW_FALU_ITINS>;
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defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", I3DNOW_FALU_ITINS>;
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defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", I3DNOW_FALU_ITINS, 1>;
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defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", I3DNOW_FALU_ITINS>;
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defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", I3DNOW_FALU_ITINS>;
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defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", I3DNOW_FALU_ITINS>;
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defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", I3DNOW_FALU_ITINS>;
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defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", I3DNOW_FALU_ITINS>;
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defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", I3DNOW_FALU_ITINS, 1>;
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defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", I3DNOW_FALU_ITINS, 1>;
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defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", I3DNOW_FCVT_I2F_ITINS>;
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defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>;
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// FIXME: Is there a better scheduler class for EMMS/FEMMS?
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let SchedRW = [WriteMicrocoded] in
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def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
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[(int_x86_mmx_femms)], IIC_MMX_EMMS>;
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// PREFETCHWT1 is supported we want to use it for everything but T0.
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def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{
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return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1();
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}]>;
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// Use PREFETCHWT1 for NTA, T2, T1.
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def PrefetchWT1Level : ImmLeaf<i32, [{
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return Imm < 3;
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}]>;
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let SchedRW = [WriteLoad] in {
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let Predicates = [Has3DNow, NoSSEPrefetch] in
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def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
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"prefetch\t$addr",
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[(prefetch addr:$addr, imm, imm, (i32 1))],
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IIC_SSE_PREFETCH>;
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def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
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[(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))],
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IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>;
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def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr",
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[(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))],
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IIC_SSE_PREFETCH>, TB, Requires<[HasPREFETCHWT1]>;
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}
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// "3DNowA" instructions
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defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">;
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defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", I3DNOW_FCVT_I2F_ITINS, "a">;
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defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", I3DNOW_FALU_ITINS, 0, "a">;
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defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", I3DNOW_FALU_ITINS, 0, "a">;
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defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", I3DNOW_PSHUF_ITINS, "a">;
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