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https://github.com/RPCS3/llvm-mirror.git
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91bb437eb8
As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
138 lines
4.5 KiB
LLVM
138 lines
4.5 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u8:
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; CHECK: clz.8b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
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ret <8 x i8> %vclz.i
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}
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define <8 x i8> @test_vclz_s8(<8 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s8:
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; CHECK: clz.8b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
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ret <8 x i8> %vclz.i
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}
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define <4 x i16> @test_vclz_u16(<4 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u16:
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; CHECK: clz.4h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
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ret <4 x i16> %vclz1.i
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}
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define <4 x i16> @test_vclz_s16(<4 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s16:
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; CHECK: clz.4h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
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ret <4 x i16> %vclz1.i
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}
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define <2 x i32> @test_vclz_u32(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u32:
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; CHECK: clz.2s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
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ret <2 x i32> %vclz1.i
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}
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define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s32:
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; CHECK: clz.2s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
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ret <2 x i32> %vclz1.i
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}
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define <1 x i64> @test_vclz_u64(<1 x i64> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u64:
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%vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
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ret <1 x i64> %vclz1.i
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}
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define <1 x i64> @test_vclz_s64(<1 x i64> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s64:
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%vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
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ret <1 x i64> %vclz1.i
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}
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define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u8:
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; CHECK: clz.16b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
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ret <16 x i8> %vclz.i
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}
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define <16 x i8> @test_vclzq_s8(<16 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s8:
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; CHECK: clz.16b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
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ret <16 x i8> %vclz.i
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}
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define <8 x i16> @test_vclzq_u16(<8 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u16:
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; CHECK: clz.8h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
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ret <8 x i16> %vclz1.i
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}
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define <8 x i16> @test_vclzq_s16(<8 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s16:
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; CHECK: clz.8h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
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ret <8 x i16> %vclz1.i
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}
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define <4 x i32> @test_vclzq_u32(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u32:
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; CHECK: clz.4s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
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ret <4 x i32> %vclz1.i
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}
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define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s32:
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; CHECK: clz.4s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
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ret <4 x i32> %vclz1.i
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}
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define <2 x i64> @test_vclzq_u64(<2 x i64> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u64:
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%vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
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ret <2 x i64> %vclz1.i
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}
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define <2 x i64> @test_vclzq_s64(<2 x i64> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s64:
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%vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
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ret <2 x i64> %vclz1.i
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}
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declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
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declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
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declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
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declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
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declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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