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7a5c52fadf
LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] llvm-svn: 147251
200 lines
4.3 KiB
LLVM
200 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+bmi,+bmi2 | FileCheck %s
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declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone
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declare i16 @llvm.cttz.i16(i16, i1) nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
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define i8 @t1(i8 %x) nounwind {
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
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ret i8 %tmp
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; CHECK: t1:
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; CHECK: tzcntl
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}
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define i16 @t2(i16 %x) nounwind {
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
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ret i16 %tmp
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; CHECK: t2:
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; CHECK: tzcntw
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}
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define i32 @t3(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
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ret i32 %tmp
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; CHECK: t3:
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; CHECK: tzcntl
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}
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define i64 @t4(i64 %x) nounwind {
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
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ret i64 %tmp
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; CHECK: t4:
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; CHECK: tzcntq
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}
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define i8 @t5(i8 %x) nounwind {
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
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ret i8 %tmp
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; CHECK: t5:
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; CHECK: tzcntl
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}
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define i16 @t6(i16 %x) nounwind {
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
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ret i16 %tmp
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; CHECK: t6:
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; CHECK: tzcntw
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}
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define i32 @t7(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK: t7:
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; CHECK: tzcntl
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}
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define i64 @t8(i64 %x) nounwind {
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
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ret i64 %tmp
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; CHECK: t8:
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; CHECK: tzcntq
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}
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define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
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%tmp1 = xor i32 %x, -1
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%tmp2 = and i32 %y, %tmp1
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ret i32 %tmp2
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; CHECK: andn32:
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; CHECK: andnl
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}
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define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
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%tmp1 = xor i64 %x, -1
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%tmp2 = and i64 %tmp1, %y
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ret i64 %tmp2
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; CHECK: andn64:
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; CHECK: andnq
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}
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define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: bextr32:
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; CHECK: bextrl
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}
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
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define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: bextr64:
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; CHECK: bextrq
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}
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
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define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: bzhi32:
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; CHECK: bzhil
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
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define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: bzhi64:
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; CHECK: bzhiq
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64) nounwind readnone
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define i32 @blsi32(i32 %x) nounwind readnone {
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%tmp = sub i32 0, %x
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%tmp2 = and i32 %x, %tmp
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ret i32 %tmp2
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; CHECK: blsi32:
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; CHECK: blsil
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}
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define i64 @blsi64(i64 %x) nounwind readnone {
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%tmp = sub i64 0, %x
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%tmp2 = and i64 %tmp, %x
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ret i64 %tmp2
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; CHECK: blsi64:
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; CHECK: blsiq
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}
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define i32 @blsmsk32(i32 %x) nounwind readnone {
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%tmp = sub i32 %x, 1
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%tmp2 = xor i32 %x, %tmp
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ret i32 %tmp2
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; CHECK: blsmsk32:
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; CHECK: blsmskl
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}
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define i64 @blsmsk64(i64 %x) nounwind readnone {
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%tmp = sub i64 %x, 1
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%tmp2 = xor i64 %tmp, %x
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ret i64 %tmp2
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; CHECK: blsmsk64:
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; CHECK: blsmskq
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}
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define i32 @blsr32(i32 %x) nounwind readnone {
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%tmp = sub i32 %x, 1
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%tmp2 = and i32 %x, %tmp
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ret i32 %tmp2
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; CHECK: blsr32:
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; CHECK: blsrl
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}
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define i64 @blsr64(i64 %x) nounwind readnone {
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%tmp = sub i64 %x, 1
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%tmp2 = and i64 %tmp, %x
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ret i64 %tmp2
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; CHECK: blsr64:
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; CHECK: blsrq
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}
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define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: pdep32:
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; CHECK: pdepl
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
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define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: pdep64:
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; CHECK: pdepq
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
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define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: pext32:
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; CHECK: pextl
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
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define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: pext64:
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; CHECK: pextq
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64) nounwind readnone
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