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https://github.com/RPCS3/llvm-mirror.git
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368 lines
11 KiB
C++
368 lines
11 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// MachineInstr.cpp
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//
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// Purpose:
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//
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//
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// Strategy:
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//
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// History:
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// 7/2/01 - Vikram Adve - Created
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//**************************************************************************/
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//************************** System Include Files ***************************/
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#include <strstream>
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//*************************** User Include Files ***************************/
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#include "llvm/Method.h"
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#include "llvm/ConstPoolVals.h"
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#include "llvm/Instruction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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//************************ Class Implementations **************************/
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// Constructor for instructions with fixed #operands (nearly all)
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MachineInstr::MachineInstr(MachineOpCode _opCode,
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OpCodeMask _opCodeMask)
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: opCode(_opCode),
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opCodeMask(_opCodeMask),
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operands(TargetInstrDescriptors[_opCode].numOperands)
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{
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assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
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}
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(MachineOpCode _opCode,
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unsigned numOperands,
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OpCodeMask _opCodeMask)
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: opCode(_opCode),
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opCodeMask(_opCodeMask),
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operands(numOperands)
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{
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}
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void
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MachineInstr::SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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Value* _val, bool isdef=false)
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{
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assert(i < operands.size());
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operands[i].Initialize(operandType, _val);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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}
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void
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MachineInstr::SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue, bool isdef=false)
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{
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assert(i < operands.size());
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operands[i].InitializeConst(operandType, intValue);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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}
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void
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MachineInstr::SetMachineOperand(unsigned int i,
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unsigned int regNum, bool isdef=false)
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{
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assert(i < operands.size());
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operands[i].InitializeReg(regNum);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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}
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void
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MachineInstr::dump(unsigned int indent) const
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{
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for (unsigned i=0; i < indent; i++)
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cout << " ";
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cout << *this;
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}
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ostream&
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operator<< (ostream& os, const MachineInstr& minstr)
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{
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os << TargetInstrDescriptors[minstr.opCode].opCodeString;
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for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++)
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os << "\t" << minstr.getOperand(i);
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#undef DEBUG_VAL_OP_ITERATOR
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#ifdef DEBUG_VAL_OP_ITERATOR
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os << endl << "\tValue operands are: ";
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for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo)
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{
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const Value* val = *vo;
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os << val << (vo.isDef()? "(def), " : ", ");
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}
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os << endl;
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#endif
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return os;
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}
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ostream&
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operator<< (ostream& os, const MachineOperand& mop)
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{
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strstream regInfo;
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if (mop.opType == MachineOperand::MO_VirtualRegister)
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regInfo << "(val " << mop.value << ")" << ends;
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else if (mop.opType == MachineOperand::MO_MachineRegister)
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regInfo << "(" << mop.regNum << ")" << ends;
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else if (mop.opType == MachineOperand::MO_CCRegister)
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regInfo << "(val " << mop.value << ")" << ends;
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switch(mop.opType)
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{
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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os << "%reg" << regInfo.str();
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free(regInfo.str());
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break;
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case MachineOperand::MO_CCRegister:
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os << "%ccreg" << regInfo.str();
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free(regInfo.str());
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break;
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case MachineOperand::MO_SignExtendedImmed:
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os << mop.immedVal;
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break;
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case MachineOperand::MO_UnextendedImmed:
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os << mop.immedVal;
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break;
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case MachineOperand::MO_PCRelativeDisp:
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os << "%disp(label " << mop.value << ")";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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return os;
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}
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//---------------------------------------------------------------------------
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// Target-independent utility routines for creating machine instructions
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//---------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated "0" register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void
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Set2OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int resultPosition)
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{
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Set3OperandsFromInstr(minstr, vmInstrNode, target,
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canDiscardResult, op1Position,
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/*op2Position*/ -1, resultPosition);
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}
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#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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unsigned
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Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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int resultPosition)
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{
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assert(op1Position >= 0);
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assert(resultPosition >= 0);
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unsigned returnFlags = 0x0;
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// Check if operand 1 is 0. If so, try to use a hardwired 0 register.
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Value* op1Value = vmInstrNode->leftChild()->getValue();
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bool isValidConstant;
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int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
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if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
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else
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{
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if (op1Value->getValueType() == Value::ConstantVal)
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{// value is constant and must be loaded from constant pool
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returnFlags = returnFlags | (1 << op1Position);
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}
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minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister,
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op1Value);
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}
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// Check if operand 2 (if any) fits in the immed. field of the instruction,
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// or if it is 0 and can use a dedicated machine register
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if (op2Position >= 0)
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{
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Value* op2Value = vmInstrNode->rightChild()->getValue();
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int64_t immedValue;
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unsigned int machineRegNum;
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MachineOperand::MachineOperandType
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op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
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/*canUseImmed*/ true,
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machineRegNum, immedValue);
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if (op2type == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperand(op2Position, machineRegNum);
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else if (op2type == MachineOperand::MO_VirtualRegister)
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{
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if (op2Value->getValueType() == Value::ConstantVal)
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{// value is constant and must be loaded from constant pool
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returnFlags = returnFlags | (1 << op2Position);
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}
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minstr->SetMachineOperand(op2Position, op2type, op2Value);
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}
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else
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{
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assert(op2type != MO_CCRegister);
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minstr->SetMachineOperand(op2Position, op2type, immedValue);
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}
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}
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// If operand 3 (result) can be discarded, use a dead register if one exists
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if (canDiscardResult && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
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else
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minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
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return returnFlags;
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}
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#endif
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void
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Set3OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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int resultPosition)
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{
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assert(op1Position >= 0);
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assert(resultPosition >= 0);
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// operand 1
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minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->leftChild()->getValue());
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// operand 2 (if any)
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if (op2Position >= 0)
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minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->rightChild()->getValue());
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// result operand: if it can be discarded, use a dead register if one exists
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if (canDiscardResult && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
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else
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minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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// Check for the common case first: argument is not constant
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//
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if (val->getValueType() != Value::ConstantVal)
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return opType;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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// unsigned constants to signed).
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//
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bool isValidConstant;
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int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant);
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if (isValidConstant)
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{
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if (intValue == 0 && target.zeroRegNum >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.zeroRegNum;
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}
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else if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode,intValue))
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{
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opType = MachineOperand::MO_SignExtendedImmed;
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getImmedValue = intValue;
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}
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}
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return opType;
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}
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void
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PrintMachineInstructions(Method* method)
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{
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cout << "\n" << method->getReturnType()
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<< " \"" << method->getName() << "\"" << endl;
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for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
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{
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BasicBlock* bb = *BI;
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cout << "\n"
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<< (bb->hasName()? bb->getName() : "Label")
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<< " (" << bb << ")" << ":"
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<< endl;
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MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0; i < mvec.size(); i++)
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cout << "\t" << *mvec[i] << endl;
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}
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cout << endl << "End method \"" << method->getName() << "\""
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<< endl << endl;
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}
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