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llvm-mirror/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll
Tim Northover 2f13163a84 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
2014-03-29 10:18:08 +00:00

16 lines
639 B
LLVM

; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
; DAGCombine to transform a conversion of an extract_vector_elt to an
; extract_vector_elt of a conversion, which saves a round trip of copies
; of the value to a GPR and back to and FPR.
; rdar://11855286
define double @foo0(<2 x i64> %a) nounwind {
; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
; CHECK-NEXT: ins.d v0[0], [[REG]][1]
%vecext = extractelement <2 x i64> %a, i32 1
%fcvt_n = tail call double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
ret double %fcvt_n
}
declare double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone