mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
15265edebe
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! llvm-svn: 161346
16 lines
369 B
LLVM
16 lines
369 B
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
; RUN: llc < %s | FileCheck %s
|
|
|
|
define i64 @test1() nounwind {
|
|
entry:
|
|
%r = call i64 @llvm.readcyclecounter()
|
|
ret i64 %r
|
|
}
|
|
|
|
; CHECK: @test1
|
|
; CHECK: mfspr 3, 268
|
|
|
|
declare i64 @llvm.readcyclecounter()
|
|
|