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268 lines
16 KiB
TableGen
268 lines
16 KiB
TableGen
//===- MBlazeSchedule5.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlaze instruction itineraries for the five stage pipeline.
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//===----------------------------------------------------------------------===//
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def MBlazePipe5Itineraries : ProcessorItineraries<
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[IF,ID,EX,MA,WB], [], [
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// ALU instruction with one destination register and either two register
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// source operands or one register source operand and one immediate operand.
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// The instruction takes one cycle to execute in each of the stages. The
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// two source operands are read during the decode stage and the result is
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// ready after the execute stage.
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InstrItinData< IIC_ALU,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 2 // result ready after two cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// ALU multiply instruction with one destination register and either two
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// register source operands or one register source operand and one immediate
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// operand. The instruction takes one cycle to execute in each of the
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// pipeline stages. The two source operands are read during the decode stage
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// and the result is ready after the execute stage.
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InstrItinData< IIC_ALUm,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 2 // result ready after two cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// ALU divide instruction with one destination register two register source
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// operands. The instruction takes one cycle to execute in each the pipeline
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// stages except the memory access stage, which takes 31 cycles. The two
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// source operands are read during the decode stage and the result is ready
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// after the memory access stage.
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InstrItinData< IIC_ALUd,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<31,[MA]> // 31 cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 33 // result ready after 33 cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Shift instruction with one destination register and either two register
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// source operands or one register source operand and one immediate operand.
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// The instruction takes one cycle to execute in each of the pipeline stages.
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// The two source operands are read during the decode stage and the result is
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// ready after the memory access stage.
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InstrItinData< IIC_SHT,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 3 // result ready after three cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Branch instruction with one source operand register. The instruction takes
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// one cycle to execute in each of the pipeline stages. The source operand is
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// read during the decode stage.
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InstrItinData< IIC_BR,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 1 ]>, // first operand read after one cycle
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// Conditional branch instruction with two source operand registers. The
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// instruction takes one cycle to execute in each of the pipeline stages. The
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// two source operands are read during the decode stage.
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InstrItinData< IIC_BRc,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Branch and link instruction with one destination register and one source
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// operand register. The instruction takes one cycle to execute in each of
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// the pipeline stages. The source operand is read during the decode stage
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// and the destination register is ready after the writeback stage.
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InstrItinData< IIC_BRl,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 4 // result ready after four cycles
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, 1 ]>, // first operand read after one cycle
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// Cache control instruction with two source operand registers. The
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// instruction takes one cycle to execute in each of the pipeline stages
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// except the memory access stage, which takes two cycles. The source
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// operands are read during the decode stage.
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InstrItinData< IIC_WDC,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<2,[MA]> // two cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Floating point instruction with one destination register and two source
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// operand registers. The instruction takes one cycle to execute in each of
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// the pipeline stages except the memory access stage, which takes two
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// cycles. The source operands are read during the decode stage and the
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// results are ready after the writeback stage.
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InstrItinData< IIC_FPU,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<2,[MA]> // two cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 5 // result ready after five cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Floating point divide instruction with one destination register and two
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// source operand registers. The instruction takes one cycle to execute in
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// each of the pipeline stages except the memory access stage, which takes 26
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// cycles. The source operands are read during the decode stage and the
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// results are ready after the writeback stage.
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InstrItinData< IIC_FPUd,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<26,[MA]> // 26 cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 29 // result ready after 29 cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Convert floating point to integer instruction with one destination
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// register and one source operand register. The instruction takes one cycle
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// to execute in each of the pipeline stages except the memory access stage,
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// which takes three cycles. The source operands are read during the decode
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// stage and the results are ready after the writeback stage.
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InstrItinData< IIC_FPUi,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<3,[MA]> // three cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 6 // result ready after six cycles
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, 1 ]>, // first operand read after one cycle
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// Convert integer to floating point instruction with one destination
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// register and one source operand register. The instruction takes one cycle
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// to execute in each of the pipeline stages except the memory access stage,
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// which takes two cycles. The source operands are read during the decode
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// stage and the results are ready after the writeback stage.
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InstrItinData< IIC_FPUf,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<2,[MA]> // two cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 5 // result ready after five cycles
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, 1 ]>, // first operand read after one cycle
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// Floating point square root instruction with one destination register and
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// one source operand register. The instruction takes one cycle to execute in
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// each of the pipeline stages except the memory access stage, which takes 25
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// cycles. The source operands are read during the decode stage and the
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// results are ready after the writeback stage.
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InstrItinData< IIC_FPUs,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<25,[MA]> // 25 cycles in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 28 // result ready after 28 cycles
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, 1 ]>, // first operand read after one cycle
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// Floating point comparison instruction with one destination register and
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// two source operand registers. The instruction takes one cycle to execute
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// in each of the pipeline stages. The source operands are read during the
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// decode stage and the results are ready after the execute stage.
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InstrItinData< IIC_FPUc,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 2 // result ready after two cycles
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, 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// FSL get instruction with one register or immediate source operand and one
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// destination register. The instruction takes one cycle to execute in each
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// of the pipeline stages. The one source operand is read during the decode
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// stage and the result is ready after the execute stage.
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InstrItinData< IIC_FSLg,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 2 // result ready after two cycles
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, 1 ]>, // first operand read after one cycle
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// FSL put instruction with either two register source operands or one
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// register source operand and one immediate operand. There is no result
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// produced by the instruction. The instruction takes one cycle to execute in
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// each of the pipeline stages. The two source operands are read during the
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// decode stage.
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InstrItinData< IIC_FSLp,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 1 // first operand read after one cycle
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, 1 ]>, // second operand read after one cycle
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// Memory store instruction with either three register source operands or two
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// register source operands and one immediate operand. There is no result
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// produced by the instruction. The instruction takes one cycle to execute in
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// each of the pipeline stages. All of the source operands are read during
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// the decode stage.
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InstrItinData< IIC_MEMs,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 1 // first operand read after one cycle
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, 1 // second operand read after one cycle
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, 1 ]>, // third operand read after one cycle
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// Memory load instruction with one destination register and either two
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// register source operands or one register source operand and one immediate
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// operand. The instruction takes one cycle to execute in each of the
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// pipeline stages. All of the source operands are read during the decode
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// stage and the result is ready after the writeback stage.
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InstrItinData< IIC_MEMl,
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[ InstrStage<1,[IF]> // one cycle in fetch stage
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, InstrStage<1,[ID]> // one cycle in decode stage
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, InstrStage<1,[EX]> // one cycle in execute stage
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, InstrStage<1,[MA]> // one cycle in memory access stage
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, InstrStage<1,[WB]>], // one cycle in write back stage
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[ 4 // result ready after four cycles
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, 1 // second operand read after one cycle
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, 1 ]> // third operand read after one cycle
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]>;
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