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2567a1faf7
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
50 lines
1.5 KiB
ArmAsm
50 lines
1.5 KiB
ArmAsm
# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
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# RUN: | FileCheck -check-prefix=CHECK-FIXUP %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INSTR %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
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# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
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# Checks that fixups that can be resolved within the same object file are
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# applied correctly
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.LBB0:
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lui t1, %hi(val)
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# CHECK-FIXUP: fixup A - offset: 0, value: %hi(val), kind: fixup_riscv_hi20
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# CHECK-INSTR: lui t1, 74565
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lw a0, %lo(val)(t1)
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# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
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# CHECK-INSTR: lw a0, 1656(t1)
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addi a1, t1, %lo(val)
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# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
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# CHECK-INSTR: addi a1, t1, 1656
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sw a0, %lo(val)(t1)
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# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_s
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# CHECK-INSTR: sw a0, 1656(t1)
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jal zero, .LBB0
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# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_jal
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# CHECK-INSTR: jal zero, -16
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jal zero, .LBB2
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# CHECK-FIXUP: fixup A - offset: 0, value: .LBB2, kind: fixup_riscv_jal
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# CHECK-INSTR: jal zero, 330996
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beq a0, a1, .LBB0
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# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_branch
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# CHECK-INSTR: beq a0, a1, -24
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blt a0, a1, .LBB1
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# CHECK-FIXUP: fixup A - offset: 0, value: .LBB1, kind: fixup_riscv_branch
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# CHECK-INSTR: blt a0, a1, 1108
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.fill 1104
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.LBB1:
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.fill 329876
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addi zero, zero, 0
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.LBB2:
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.set val, 0x12345678
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# CHECK-REL-NOT: R_RISCV
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