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a70016c8d5
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}load_i8_sext_private:
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; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i8_sext_private(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = alloca i8, addrspace(5)
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%tmp1 = load i8, i8 addrspace(5)* %tmp0
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%tmp2 = sext i8 %tmp1 to i32
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i8_zext_private:
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; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i8_zext_private(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = alloca i8, addrspace(5)
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%tmp1 = load i8, i8 addrspace(5)* %tmp0
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%tmp2 = zext i8 %tmp1 to i32
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i16_sext_private:
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; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i16_sext_private(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = alloca i16, addrspace(5)
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%tmp1 = load i16, i16 addrspace(5)* %tmp0
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%tmp2 = sext i16 %tmp1 to i32
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i16_zext_private:
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; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = alloca i16, addrspace(5)
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%tmp1 = load volatile i16, i16 addrspace(5)* %tmp0
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%tmp2 = zext i16 %tmp1 to i32
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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