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24 lines
996 B
LLVM
24 lines
996 B
LLVM
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
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; The earliest R600 GPUs have a slightly different encoding than the rest of
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; the VLIW4/5 GPUs.
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; EG: {{^}}test:
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; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
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; R600: {{^}}test:
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; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
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define amdgpu_ps void @test(<4 x float> inreg %reg0) {
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entry:
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%r0 = extractelement <4 x float> %reg0, i32 0
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%r1 = extractelement <4 x float> %reg0, i32 1
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%r2 = fmul float %r0, %r1
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%vec = insertelement <4 x float> undef, float %r2, i32 0
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call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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ret void
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}
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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