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6705a324ed
The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
162 lines
5.1 KiB
YAML
162 lines
5.1 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @fold_fi_vgpr() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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define amdgpu_kernel void @fold_vgpr_fi() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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define amdgpu_kernel void @fold_sgpr_fi() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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define amdgpu_kernel void @fold_fi_sgpr() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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define amdgpu_kernel void @fold_fi_imm() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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define amdgpu_kernel void @fold_imm_fi() {
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%alloca = alloca [4 x i32], addrspace(5)
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ret void
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}
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...
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# GCN-LABEL: name: fold_fi_vgpr{{$}}
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# GCN: %1:vgpr_32 = IMPLICIT_DEF
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
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name: fold_fi_vgpr
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = IMPLICIT_DEF
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%2, $vcc = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: fold_vgpr_fi{{$}}
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# GCN: %1:vgpr_32 = IMPLICIT_DEF
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
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name: fold_vgpr_fi
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = IMPLICIT_DEF
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%2, $vcc = V_ADD_CO_U32_e64 %1, %0, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: fold_sgpr_fi{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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# GCN: %1:sgpr_32 = IMPLICIT_DEF
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 %1, %0, implicit-def $vcc, implicit $exec
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name: fold_sgpr_fi
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: sgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = IMPLICIT_DEF
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%2, $vcc = V_ADD_CO_U32_e64 %1, %0, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: fold_fi_sgpr{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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# GCN: %1:sgpr_32 = IMPLICIT_DEF
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 %1, %0, implicit-def $vcc, implicit $exec
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name: fold_fi_sgpr
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: sgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = IMPLICIT_DEF
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%2, $vcc = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0
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...
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# TODO: Should probably prefer folding immediate first
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# GCN-LABEL: name: fold_fi_imm{{$}}
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# GCN: %1:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
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name: fold_fi_imm
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = V_MOV_B32_e32 999, implicit $exec
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%2, $vcc = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: fold_imm_fi{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 999, %0, implicit-def $vcc, implicit $exec
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name: fold_imm_fi
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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stack:
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- { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
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%1 = V_MOV_B32_e32 999, implicit $exec
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%2, $vcc = V_ADD_CO_U32_e64 %1, %0, 0, implicit $exec
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S_ENDPGM 0
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